AMD Patch To Use MWAIT Instead Of HALT For Certain Cases Yield A ~21% Improvement

[phoronix]

Phoronix: AMD Patch To Use MWAIT Instead Of HALT For Certain Cases Yield A ~21% Improvement

As a Linux kernel change for benefiting AMD CPUs going back to Zen 1 and for matching behavior Intel has had in place since the Core 2 times, AMD submitted a patch for having the Linux kernel use the MWAIT instruction instead of HALT for when the system isn't using the CPU idle driver either for C-states being disabled by the BIOS or the driver not part of the kernel build. In turn this can lead to around a 21% improvement in exit latency on affected systems...

https://www.phoronix.com/scan.php?page=news_item&px=AMD-MWAIT-Over-HALT-2022

[Venemo]

Typo:

The code comment in the screenshot says: "Intel Core 2 and older", but the article text says: "Intel Core 2 and later".

[richardnpaul]

Typo:

The code comment in the screenshot says: "Intel Core 2 and older", but the article text says: "Intel Core 2 and later".

That's from the Linux source code so you could submit a patch to fix that comment 😁

[Jabberwocky]

IIRC MWAIT caused problems on early Zen1 CPUs... which is why people disabled C-states in the BIOS.

From what I can tell this will ignore that BIOS setting and could cause problems for people that could not go through the RMA process.

Could this new change be disabled by setting "idle=nomwait" or is this not a concern anymore?

[8r34k0u7_57y13]

IIRC MWAIT caused problems on early Zen1 CPUs... which is why people disabled C-states in the BIOS.

From what I can tell this will ignore that BIOS setting and could cause problems for people that could not go through the RMA process.

Could this new change be disabled by setting "idle=nomwait" or is this not a concern anymore?

AFAIK, this isn't a processor issue per-se, it's a mainboard issue.
Mainboards with an external clock generator will have issues with MWAIT and C6, cheaper mainboards that use the SoC's PLL, don't have that problem.

[LumielGR]

AFAIK, this isn't a processor issue per-se, it's a mainboard issue.

Do you have any source on that so I can read and see if my motherboard is affected? The erratum 1109 of the revision guide for family 17h states:

Under a highly specific and detailed set of internal timing conditions, the MWAIT instruction may cause a thread to hang in SMT (Simultaneous Multithreading) Mode
No fix planned

[arQon]

This may be more interesting than it's currently being treated here. While 600ns isn't going to be meaningful to anyone (tho PH has probably rebuilt his kernel with the change already :P) the high-range values are probably quite noticeable under some circumstances, and a laptop that's constantly slamming cores offline to save power will give you several thousand chances a day to hit one that is.

[Jabberwocky]

AFAIK, this isn't a processor issue per-se, it's a mainboard issue.
Mainboards with an external clock generator will have issues with MWAIT and C6, cheaper mainboards that use the SoC's PLL, don't have that problem.

Do you have any sources for that? I had that issue with the following motherboards (and PSUs):

• ASUS Prime X370-PRO (Corsair RM550x)
• ASRock Fatal1ty X370 Professional Gaming (Sea Sonic PRIME Ultra 1000 Titanium)
• ASRock X470 Taichi Ultimate (Corsair HX750i Titanium)

I'm on the same page as LumielGR because AMD said it's a processor issue.

That said, I have not experienced any issues in a long time though even with the early Zen1 CPUs that I was not able to RMA.

[MorrisS.]

Why the previous AMD cpus which integrates the MWAIT instruction are not supported?