Linux Kernel Seeing Workaround Revived For Buggy Micron NAND Block Erase Behavior

[phoronix]

Phoronix: Linux Kernel Seeing Workaround Revived For Buggy Micron NAND Block Erase Behavior

A new patch series has been revived from work originally published by Micron back in 2018 for dealing with the behavior on their planar 2D NAND devices where in rare cases when issuing block erase commands, the flash block might not actually be erased and this could lead to further problems down the road when touching said block...

http://www.phoronix.com/scan.php?page=news_item&px=Micron-NAND-Block-Erase-V5

[coder]

Uh, so I guess this affects Crucial SSDs? I have a lot of Crucial SSDs, spanning the entire last decade. So, I wonder which ones... ?

Then again, are we really talking about like SATA SSDs, or maybe this is for embedded devices using raw NAND?

drivers/mtd/nand/raw/internals.h | 3 +-
drivers/mtd/nand/raw/nand_base.c | 87 ++++++++++++++++++----
drivers/mtd/nand/raw/nand_hynix.c | 2 +-
drivers/mtd/nand/raw/nand_macronix.c | 10 +--
drivers/mtd/nand/raw/nand_micron.c | 104 ++++++++++++++++++++++++++-
include/linux/mtd/rawnand.h | 40 +++++++----

[keelung]

Uh, so I guess this affects Crucial SSDs? I have a lot of Crucial SSDs, spanning the entire last decade. So, I wonder which ones... ?
...

It's about raw nand but managed nand, SSDs are the latter.
For using raw nand, there must be a controller to control raw nand chip.
A controller is hosted in a host(a SoC chip usually), in a SSD disk, a USB disk, even a SD Card and so on.

RAW NAND vs Managed NAND: https://www.micron.com/products/nand...the-right-nand
Pictures of RAW NAND chip and it's controller: https://www.rs-online.com/designspar...out-nand-flash

And, we are suffering abused power-cut actions in productions, hope these patches help us.