Libre RISC-V Accelerator Secures 300k EUR In Grants, Still Undecided About The ISA

[phoronix]

Phoronix: Libre RISC-V Accelerator Secures 300k EUR In Grants, Still Undecided About The ISA

Libre RISC-V, the project aiming to create an open-source accelerator that would run a Vulkan software renderer in being an "open-source GPU" aiming for just 25 FPS @ 720p or 5~6 GFLOPS, has managed to secure 300k EUR in grants for their work...

http://www.phoronix.com/scan.php?page=news_item&px=Libre-RISC-V-300k-Grants

[bachchain]

I can definitely see how, for a project called "Libre RISC-V", the ISA is a point of debate.
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[uid313]

Will this use LLVMpipe?
Is it even feasible to make a GPU built on RISC-V or POWER? Is it even a good idea?
Intel already tried to make an GPU based on x86 called Larrabee, and they abandoned it.

[Michael]

Will this use LLVMpipe?
Is it even feasible to make a GPU built on RISC-V or POWER? Is it even a good idea?
Intel already tried to make an GPU based on x86 called Larrabee, and they abandoned it.

Their current plan is focused on Kazan for Vulkan, but LLVMpipe theoretiically would work too.

Keep in mind they are setting very low performance expectations (~25 FPS at 720p) compared to Intel and other efforts aiming for legitimately high performance.

[pkese]

What's the point of building a 5-6 GFLOPS CPU/GPU (considering that a $35 Raspberry PI GPU has 24 GFLOPS).

It seems that the technological agenda here is way behind the political one (including bashing of RISC-V ISA).

[curaga]

@pkese: The point of this SoC is to create an entirely libre processor. Source code for everything, verifiable, customizable - you can be sure there are no backdoors, that the chip is doing what you want it to. You can hack on it. The initial performance targets are for a cheap node (180nm costs a tiny part of modern nodes) and low power budget - it's not going to be a performance killer, it's the first implementation. However it will fill the goal of a libre processor, and improvements to both design and smaller nodes will come.

[WolfpackN64]

@pkese: The point of this SoC is to create an entirely libre processor. Source code for everything, verifiable, customizable - you can be sure there are no backdoors, that the chip is doing what you want it to. You can hack on it. The initial performance targets are for a cheap node (180nm costs a tiny part of modern nodes) and low power budget - it's not going to be a performance killer, it's the first implementation. However it will fill the goal of a libre processor, and improvements to both design and smaller nodes will come.

This. If you're starting with this kind of proof of concept Vulkan accelerator, better to try something you can realistically produce as a first generation product with realistic performance expectations and then work from there.

[pkese]

@pkese: The point of this SoC is to create an entirely libre processor.

There already exist a bunch of opensource RISC-V implementations: https://github.com/riscv/riscv-cores-list
How about taking one of those and add the Vector extension to it?
The Pulpino ARA implementation reached 34 GFLOPS with dual precision (67 DP-GFLOPS/W) and had reached silicon implementation.

I'm trying to understand how is this different (i.e. what's the innovative contribution, besides the 'not invented here' syndrome)...

[aht0]

curaga it's impossible to implement.

[curaga]

There already exist a bunch of opensource RISC-V implementations: https://github.com/riscv/riscv-cores-list How about taking one of those and add the Vector extension to it?

According to lkcl in a previous phoronix thread, many of those require proprietary compilers, and the remaining ones were made in some hard to work with custom language. This project would be usable entirely with FOSS.