Updated AMD Zen Scheduler Model Lands For LLVM 6.0

[phoronix]

Phoronix: Updated AMD Zen Scheduler Model Lands For LLVM 6.0

With the soon-to-be-released LLVM 5.0 there is the initial AMD Zen scheduler model for the compiler to benefit Ryzen / EPYC processors. But now already hitting the LLVM development code for LLVM 6.0 is a revised scheduler model...

http://www.phoronix.com/scan.php?page=news_item&px=Znver1-Scheduler-Update-LLVM6

[Azpegath]

Do the new generation of AMD processors support instruction sets as AVX? Or something similar?

[sandain]

Wikipedia says so:

All models support: x87, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, CLMUL, AVX, AVX2, FMA, CVT16/F16C, ABM, BMI1, BMI2, SHA.

[Tomin]

Do the new generation of AMD processors support instruction sets as AVX? Or something similar?

Yes. Already Bulldozer (e.g. FX series) supported AVX and Excavator got AVX2. I think all current AMD processors support at least some form of AVX (AVX2 for anything on AM4 or with Zen).

[FireBurn]

Could you do tests against this commit and the commit before it to see if it speed things up at all

[smitty3268]

Do the new generation of AMD processors support instruction sets as AVX? Or something similar?

Yes, but the AVX2 support is only at half speed (aka the same as full rate but half data-width size AVX)

[Chewi]

What's GCC's znver1 like, at the moment? A short while ago, it was poorly tuned so I've been wondering if it's improved, particular as 7.2.0 has just been released.

[bridgman]

Yes, but the AVX2 support is only at half speed (aka the same as full rate but half data-width size AVX)

Huh ? AVX2 support is typically the same speed as Intel except for FMA (which is half speed as you say). AVX (128 bit) instructions can sometimes run faster on Ryzen because it has 4x 128-bit ALUs instead of 2x 256-bit.

This is just my casual understanding from looking at benchmark results, but comments from Agner Fog and others seem to support it.

[Duve]

What's GCC's znver1 like, at the moment? A short while ago, it was poorly tuned so I've been wondering if it's improved, particular as 7.2.0 has just been released.

That is a very good question that I would also like an answer to...
My honest guess is that there will be changes on 8.0 since that is currently being developed, but I would be wrong about that.

[smitty3268]

AVX (128 bit) instructions can sometimes run faster on Ryzen because it has 4x 128-bit ALUs instead of 2x 256-bit.

That's all I'm saying. If you convert AVX code to AVX2 it will run twice as fast on Intel, but the same speed on Ryzen because you have half the ALUs. Well, more like 50% faster on Intel because apparently their chips get heavily heat-constrained when you try to do that.