Clang 20 Compiler Adds Support For Xtensa CPU Target

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  • Developer12
    replied
    Originally posted by Gamer1227 View Post

    Well, it is nice now that Xtensa can use upstream Clang now, but probably only the ESP developers will be maintaining that backend, while with RISCV they can enjoy the work of companies like SiFive and others that already contribute to maintain software for RISCV.
    The ESP developers hardly contribute to anything afaik. it's the ESP community, which it turns out is large. As long as espressif continue to make xtensa chips, they will continue to work.

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  • brad0
    replied
    The backend work has more or less just started. It'll be quite some time before this will be usable. Look back around Clang LLVM / Clang 22.

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  • Gamer1227
    replied
    Originally posted by Developer12 View Post

    Well, that forking may now be coming to an end.
    Well, it is nice now that Xtensa can use upstream Clang now, but probably only the ESP developers will be maintaining that backend, while with RISCV they can enjoy the work of companies like SiFive and others that already contribute to maintain software for RISCV.

    Leave a comment:


  • Developer12
    replied
    Originally posted by Gamer1227 View Post

    Only the ESP32-S3 have a floating point unit, the base ESP32 and S2 dont have a FPU just like the RISCV products, because it is not demanded by most of their customers, those are low power IoT machines.

    The RISCV products have lower integer performace, because the engineers decided that power consumption and price is more important than speed for most customers, CPU design is full of tradeoffs.

    ISA is not related to core performace, ARM coress go from tiny microcontrollers like the Cortex M0+, to big monsters like the Apple M4 cores.

    The 1 advantage of RISCV over Xtensa, is that RISCV have upstream support in GCC, Clang, GDB and other important software, while Xtensa needs versions forked by ESP.
    Well, that forking may now be coming to an end.

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  • Gamer1227
    replied
    Originally posted by wosgien View Post

    XTensa cores are very good and support float computation - something not all Risc-V version do.
    And Risc-V version tend to be somehow less performant event in integer.
    But they are cheaper ... and float number are not needed in most products.

    So the conversion is on the way.
    Only the ESP32-S3 have a floating point unit, the base ESP32 and S2 dont have a FPU just like the RISCV products, because it is not demanded by most of their customers, those are low power IoT machines.

    The RISCV products have lower integer performace, because the engineers decided that power consumption and price is more important than speed for most customers, CPU design is full of tradeoffs.

    ISA is not related to core performace, ARM coress go from tiny microcontrollers like the Cortex M0+, to big monsters like the Apple M4 cores.

    The 1 advantage of RISCV over Xtensa, is that RISCV have upstream support in GCC, Clang, GDB and other important software, while Xtensa needs versions forked by ESP.

    Leave a comment:


  • wosgien
    replied
    Originally posted by Developer12 View Post
    The RISC-V versions of the chips haven't seen as much uptake or traction. RISC-V is still very niche.
    No, they are been used for products. Theyr is some latency though: you can't swap Xtensa version and risc-v version.

    XTensa cores are very good and support float computation - something not all Risc-V version do.
    And Risc-V version tend to be somehow less performant event in integer.
    But they are cheaper ... and float number are not needed in most products.

    So the conversion is on the way.

    Leave a comment:


  • Developer12
    replied
    Leave it to Michael to be completely ignorant of the most popular embedded processor made since the AVR atmega328p. There are ungodly numbers of ESP32s being made and deployed, all using xtensa CPUs. There is literally nothing else in the market.

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  • Developer12
    replied
    Originally posted by Gamer1227 View Post

    For the next few years.

    ESP has stopped developing new Xtensa chips a few years, now only doing RISC-V. Actually lots of niche ISAs have been dying recently, thanks to RISC-V being very modular and allowing custom instructions.

    I wonder for how long they will keep producing the Xtensa products, to support legacy code.
    The RISC-V versions of the chips haven't seen as much uptake or traction. RISC-V is still very niche.

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  • Developer12
    replied
    Originally posted by caligula View Post

    Hasn't it been mostly closed source? I think one of the issues with ESP/ESP32 is that the SDK and dev toolchain were closed source unlike Arduino / STMIcro / RPi MCUs..
    The SDK is 100% open source with two (really one) exception: The wifi/bluetooth driver.

    That's changing though. At CCC this year was a presentation on the rapidly-maturing reverse-engineered wifi driver for the ESP's wifi. After letting the blob do radio calibration (still a very complex job) they can now send and receive packets over wifi.

    Incidentally, this effort is largely (entirely?) written in rust, which might explain why LLVM support for the ESP's CPU came a year before it was added to clang. You don't need clang support to target the ESP with rust, only basic LLVM backend support.

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  • klokik
    replied
    Don't forget all the current Intel and AMD SoCs using Xtensa HiFi Audio DSPs running Sound Open Firmware

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