Clang 20 Compiler Adds Support For Xtensa CPU Target

[wosgien]

The RISC-V versions of the chips haven't seen as much uptake or traction. RISC-V is still very niche.

No, they are been used for products. Theyr is some latency though: you can't swap Xtensa version and risc-v version.

XTensa cores are very good and support float computation - something not all Risc-V version do.
And Risc-V version tend to be somehow less performant event in integer.
But they are cheaper ... and float number are not needed in most products.

So the conversion is on the way.

[Gamer1227]

XTensa cores are very good and support float computation - something not all Risc-V version do.
And Risc-V version tend to be somehow less performant event in integer.
But they are cheaper ... and float number are not needed in most products.

So the conversion is on the way.

Only the ESP32-S3 have a floating point unit, the base ESP32 and S2 dont have a FPU just like the RISCV products, because it is not demanded by most of their customers, those are low power IoT machines.

The RISCV products have lower integer performace, because the engineers decided that power consumption and price is more important than speed for most customers, CPU design is full of tradeoffs.

ISA is not related to core performace, ARM coress go from tiny microcontrollers like the Cortex M0+, to big monsters like the Apple M4 cores.

The 1 advantage of RISCV over Xtensa, is that RISCV have upstream support in GCC, Clang, GDB and other important software, while Xtensa needs versions forked by ESP.

[Developer12]

Only the ESP32-S3 have a floating point unit, the base ESP32 and S2 dont have a FPU just like the RISCV products, because it is not demanded by most of their customers, those are low power IoT machines.

The RISCV products have lower integer performace, because the engineers decided that power consumption and price is more important than speed for most customers, CPU design is full of tradeoffs.

ISA is not related to core performace, ARM coress go from tiny microcontrollers like the Cortex M0+, to big monsters like the Apple M4 cores.

The 1 advantage of RISCV over Xtensa, is that RISCV have upstream support in GCC, Clang, GDB and other important software, while Xtensa needs versions forked by ESP.

Well, that forking may now be coming to an end.

[Gamer1227]

Well, that forking may now be coming to an end.

Well, it is nice now that Xtensa can use upstream Clang now, but probably only the ESP developers will be maintaining that backend, while with RISCV they can enjoy the work of companies like SiFive and others that already contribute to maintain software for RISCV.

[brad0]

The backend work has more or less just started. It'll be quite some time before this will be usable. Look back around Clang LLVM / Clang 22.