LLVM Merges Support The For Tenstorrent TT-Ascalon-D8 RISC-V CPU

[phoronix]

Phoronix: LLVM Merges Support The For Tenstorrent TT-Ascalon-D8 RISC-V CPU

Adding to the interesting code building up for next spring's release of the LLVM 20 compiler stack is having the Tenstorrent TT-Ascalon D8 as the newest RISC-V processor target...

https://www.phoronix.com/news/LLVM-20-Tenstorrent-Ascalon

[ayumu]

This is the real deal, by a strong engineering team led by the main architect behind Apple's M1's design.

I am looking forward to seeing it benchmarked.

[ms178]

The CPU (and even more so the GPU) market is in dire need of more innovation and more competition. The sooner we get there, the better.

[Gamer1227]

Is that right? 8-wide decoder, that is as wide as a Zen5 core or a M1 big core.

But probably will take a lot of time to complete, so there is that.

[Guiorgy]

The title has a typo, "the" and "for" are mixed.

[ayumu]

Is that right? 8-wide decoder, that is as wide as a Zen5 core or a M1 big core.

And IPC higher than Zen5 as per slides from a couple years ago.

But probably will take a lot of time to complete, so there is that.

There was an announcement early last year that it had been licensed by LG to use in their Smart TVs.

Design must have been complete for longer. But from IP to actual chips there's usually a gap spawning years.