MIPS P8700 RISC-V CPU Support Posted For LLVM Compiler

[phoronix]

Phoronix: MIPS P8700 RISC-V CPU Support Posted For LLVM Compiler

MIPS has begun working on the open-source compiler toolchain support for their P8700 RISC-V based processors. Initial patches posted today bring-up the MIPS P8700 RISC-V support for the LLVM compiler stack...

https://www.phoronix.com/news/MIPS-P8700-RISC-V-LLVM

[ayumu]

the P8700 introduces two new instructions of its own around conditional moves "mipscmov" and a load/store pair instruction "mipslsp".

If not obvious enough, these are not standard RISC-V instructions, but custom extensions by MIPS.

Notably, the foundation has its own conditional ops (Zicond) and load/store pair (RVS-1948) extensions.

https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154861/RISC-V+Specification+Status

RVS-1948 (load/store pair) is currently under public review.

Zicond was ratified in 2023.

[davidlt]

The initial documentation for this seems to be released on "January 31, 2022". So it took 2+ or 3+ years before this reached GA. This also targets automotive market thus probably making development quite long.

[microcode]

If not obvious enough, these are not standard RISC-V instructions, but custom extensions by MIPS.

Notably, the foundation has its own conditional ops (Zicond) and load/store pair (RVS-1948) extensions.

https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154861/RISC-V+Specification+Status

RVS-1948 (load/store pair) is currently under public review.

Zicond was ratified in 2023.

Zicond is incorporated into the unprivileged spec but not widely used, and RVS-1948/‘Zilsd’ is only applicable to RV32, so would not be usable in P8700 anyway.

[microcode]

The initial documentation for this seems to be released on "January 31, 2022". So it took 2+ or 3+ years before this reached GA. This also targets automotive market thus probably making development quite long.

One other issue with the product is that instead of making a slightly smarter decoder, or supporting the standard extension, they introduced custom instructions for conditional move, and are presumably encouraging integrators to build all of their software with this custom target? Seems like a bit of a distraction but what would I know.

[ayumu]

Zicond is incorporated into the unprivileged spec but not widely used

It's part of RVA23, so it will be. Once there's hardware that supports that. Typically three years from spec to hardware.

and RVS-1948/‘Zilsd’ is only applicable to RV32, so would not be usable in P8700 anyway.

64-bit RISC-V was already the most dense 64bit ISA at the first spec ratifications in 2019.

32-bit RISC-V was not (thumb2 used to be more dense), thus many 64bit-specific opcodes were reused as density-increasing extensions in 32bit.

[Gamer1227]

One other issue with the product is that instead of making a slightly smarter decoder, or supporting the standard extension, they introduced custom instructions for conditional move, and are presumably encouraging integrators to build all of their software with this custom target? Seems like a bit of a distraction but what would I know.

It is a automotive CPU, so development started way before the standard extensions were ratified.

Also, not all software needs to support these extensions, they are just extra stuff for software that wants some performace boost, other software can just use standard instructions.

[microcode]

It's part of RVA23, so it will be. Once there's hardware that supports that. Typically three years from spec to hardware.



64-bit RISC-V was already the most dense 64bit ISA at the first spec ratifications in 2019.

32-bit RISC-V was not (thumb2 used to be more dense), thus many 64bit-specific opcodes were reused as density-increasing extensions in 32bit.

My point was Zilsd is not a solution for P8700, there is no standard extension which does this on RV64.

[ayumu]

My point was Zilsd is not a solution for P8700, there is no standard extension which does this on RV64.

It's perfectly possible to compile code w/o the custom extension. RV64 does not need it, it already is the most dense 64bit ISA.

I also won't be surprised when future MIPS 64bit microarchitectures remove the custom extension. When P8700 was designed, which must have been years ago, Zilsd was likely being drafted still, and the decision to make it 32bit only had likely not been made.

[microcode]

It's perfectly possible to compile code w/o the custom extension. RV64 does not need it, it already is the most dense 64bit ISA.

I also won't be surprised when future MIPS 64bit microarchitectures remove the custom extension. When P8700 was designed, which must have been years ago, Zilsd was likely being drafted still, and the decision to make it 32bit only had likely not been made.

You missed the point though, you were mentioning that they had a custom extension making it out like the RV32-only one you mentioned was at all comparable...