Apple M2 Support Added To Upstream LLVM Along With The A15, A16

[name99]

I considered that, but I still think things like the ratio of different execution ports can have a measurable effect. Maybe in just a few compute-heavy corner cases, but I'm not convinced it's irrelevant.


Interesting. I'd have expected their OoO would handle that, too. I guess, if you can just patch the compiler, then why bother doing it in hardware?

I think you do not understand/appreciate what instruction fusion does.

[name99]

Not sure where you got the 10% figure, but it's not consistent with what ARM reported (as I quoted in comment 13).

In any case, I just think it's interesting. I don't have a dog in this fight -- just a bemused observer.

The comparison is not SVE vs NEON, it is SVE vs Macroscalar (or whatever does as opposed to SVE, and assuming code optimized for SVE ideas.)

[coder]

I think you do not understand/appreciate what instruction fusion does.

Uh, reduces instructions by combining 2 simpler ops into a single complex one? I get that it's better to do it earlier, so you occupy less space in caches, ROB, etc.

[name99]

Uh, reduces instructions by combining 2 simpler ops into a single complex one? I get that it's better to do it earlier, so you occupy less space in caches, ROB, etc.

Fusion is generally done at Decode time. Decode is part of the In-Order front-end of the machine. For fusion to happen, two fusible instructions have to be recognized as such, which essentially means they need to be sequential in the instruction stream.