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Open-Source FPGA-Based RISC-V GPGPU That Supports OpenCL 1.2

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  • Open-Source FPGA-Based RISC-V GPGPU That Supports OpenCL 1.2

    Phoronix: Open-Source FPGA-Based RISC-V GPGPU That Supports OpenCL 1.2

    While there was the Libre RISC-V GPU effort aiming to provide an open-source GPU accelerator based on RISC-V, it ultimately turned into Libre-SOC with a focus now on the POWER ISA. Meanwhile Vortex is continuing to mature as an open-source, FPGA-based RISC-V GPGPU processor...

    https://www.phoronix.com/scan.php?pa...x-RISC-V-GPGPU

  • #2
    Interesting. But, if you've got a big FPGA and want to use OpenCL on it, you're better off targeting the raw FPGA, itself.


    Maybe the ultimate goal isn't targeting FPGAs, but rather to build an ASIC?

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    • #3
      I would use the the RISCV z{f,d,h}-in-x extension for that https://www.youtube.com/watch?v=F5ZuaQh43tE

      Comment


      • #4
        Originally posted by coder View Post
        Interesting. But, if you've got a big FPGA and want to use OpenCL on it, you're better off targeting the raw FPGA, itself.

        Maybe the ultimate goal isn't targeting FPGAs, but rather to build an ASIC?
        That's hard, and regular openCL through LLVM is easy.

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        • #5
          Ok, so back of the envelope math says this is performance roughly on par with 2008-2009? That's not great, but it's not terrible either.

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          • #6
            Originally posted by Developer12 View Post
            That's hard, and regular openCL through LLVM is easy.
            Huh?

            I mean, if you have one of these FPGA cards, you can get tools from Intel for running OpenCL directly on it. Instead of having a bunch of soft cores that run generated RISC-V code, Intel's OpenCL compiler synthesizes your OpenCL kernels directly into gate configurations.

            So, the only way what they're doing makes much sense to me is if they're just prototyping on a FPGA, with the eventual plan to fab it into an ASIC.

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            • #7
              Originally posted by coder View Post
              Huh?

              I mean, if you have one of these FPGA cards, you can get tools from Intel for running OpenCL directly on it. Instead of having a bunch of soft cores that run generated RISC-V code, Intel's OpenCL compiler synthesizes your OpenCL kernels directly into gate configurations.

              So, the only way what they're doing makes much sense to me is if they're just prototyping on a FPGA, with the eventual plan to fab it into an ASIC.
              Resynthesizing an FPGA requires a whole proprietary toolchain and considerable resources, where as targeting an openCL API does not.

              FPGAs are much cheaper and more accessible than the cost of manufacturing an ASIC. LibreBMC for example runs on an FPGA and has no plans to move to an ASIC, with the side effect of being more open-source friendly.

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              • #8
                Originally posted by Developer12 View Post
                Resynthesizing an FPGA requires a whole proprietary toolchain and considerable resources, where as targeting an openCL API does not.
                Synthesizing this soft accelerator for a FPGA does. So, you're stuck with a proprietary toolchain, either way.

                Originally posted by Developer12 View Post
                FPGAs are much cheaper and more accessible than the cost of manufacturing an ASIC.
                But performance on a FPGA is bad enough that it's basically pointless. I could get better throughput from simply running the OpenCL code on a modern CPU!

                Comment


                • #9
                  A paper explaining in a little more detail what Vortex is all about (Beside being a good subject for research papers)
                  https://arxiv.org/pdf/2002.12151.pdf

                  1. By hooking into POCL it makes itself not purely academic, you get a real library and complier.

                  2. Right now the major effort looks to be in building hardware primitives to allow the SIMT model (warp/weave/thread) of execution with few changes to the ISA. With the payoff of better energy efficiency workloads where CUDA/openCL is now used.

                  Originally posted by rene View Post
                  I would use the the RISCV z{f,d,h}-in-x extension for that https://www.youtube.com/watch?v=F5ZuaQh43tE
                  It's likely any commercial riscv based gpu would need both SIMT primatives, and use the primary architectural registers for floating point values. Given each SIMT thread has private registers, efficient use of the register file is critical.

                  And at the moment it's not a commercial project, just research and ideals. And not anywhere near being a full fledged GPU, not least of which lacking fixed function pipelines and the needed. byte wrangling instructions. GPGPU basicly means "you know those things we do with GPU's that arent actually related to graphics at all? Ya, we try to do that".


                  WorBlux
                  Senior Member
                  Last edited by WorBlux; 01 December 2021, 02:28 AM.

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                  • #10
                    Typo:

                    Originally posted by phoronix View Post
                    This general purpose GPU makes use of the RISV-V RV32IMF 32-bit ISA and can yield up to 1024 threads at 250MHz.

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