OpenBLAS 0.3.13 Released With A RISC-V Port, POWER10 Optimizations

[phoronix]

Phoronix: OpenBLAS 0.3.13 Released With A RISC-V Port, POWER10 Optimizations

OpenBLAS 0.3.13 was released today as the newest update to this leading open-source BLAS (and LAPACK) implementation...

http://www.phoronix.com/scan.php?pag....3.13-Released

[baryluk]

What RISC-V CPUs actually have RISC-V Vector Extension?

[brucehoult]

What RISC-V CPUs actually have RISC-V Vector Extension?

Nothing a retail chip customer can buy yet.

As noted in the article, Alibaba's C910V, which apparently is already in use in their cloud facility, implements an early draft version, which is incompatible with the eventual 1.0.

If you're someone making chips, you can license RISC-V cores from Andes (NZ27V announced in September) and SiFive (VIU75 announced in October) today. Right now they have implemented late draft versions of the eventual 1.0 standard (which will probably change very little now) that you can get started with in simulations and FPGAs and start writing software for. They promise that by the time you tape-out your chip in 6 or 12 months their RTL will fully implement the ratified 1.0 standard.

Those chips will start to actually ship in 12 to 30 months from now.

[coder]

I'm curious (but not enough to go sifting through commit logs) who is doing the POWER work. IBM, still? And why -- still chasing the HPC and ML markets?

[baryluk]

I'm curious (but not enough to go sifting through commit logs) who is doing the POWER work. IBM, still? And why -- still chasing the HPC and ML markets?

IBM doesn't want to relay on Intel and AMD to dictated stuff for them. They and many others want to have safety of having other options. Also POWER has some advantages over available x86 solutions, including in DB, Server and HPC and financial world. x86 is trying to do everything with a lot of compromises, POWER is focusing only on few higher end systems, which dictate everything, wide SMT, memory, SMP, reliability, floating point decimal support, etc. Plus there are political / security aspects of keeping POWER alive.

[WorBlux]

IBM doesn't want to relay on Intel and AMD to dictated stuff for them. They and many others want to have safety of having other options. Also POWER has some advantages over available x86 solutions, including in DB, Server and HPC and financial world. x86 is trying to do everything with a lot of compromises, POWER is focusing only on few higher end systems, which dictate everything, wide SMT, memory, SMP, reliability, floating point decimal support, etc. Plus there are political / security aspects of keeping POWER alive.

IBM has actually opened up the ISA, and have released verilog level code for A2I, A2O, and microwatt, a VHDL softcore. The libreSOC project is currently targeting the POWER 3.1 ISA. Also POWER 10 is right around the cornet. My expectation is that Power will continue to show up in the next five -ten years and not necessarily in the HPC/mainframe space.

[coder]

IBM doesn't want to relay on Intel and AMD to dictated stuff for them. They and many others want to have safety of having other options.

I know I didn't exactly ask that in the most neutral way, but I wasn't trying to start a flame war. I'm glad that POWER is still in the game, even if ARM is eating into their marketshare and RISC-V is eating into their mindshare.

Getting back to my question, was it actually IBM doing this work? Not that it matters, I'm just curious.

[baryluk]

I know I didn't exactly ask that in the most neutral way, but I wasn't trying to start a flame war. I'm glad that POWER is still in the game, even if ARM is eating into their marketshare and RISC-V is eating into their mindshare.

Getting back to my question, was it actually IBM doing this work? Not that it matters, I'm just curious.

Yes, POWER10 optimizations were done by Rajalakshmi Srinivasaraghavan from IBM (she also made a many POWER stuff in gcc, glibc, including optimisations and vectorisations), with some minor fixes from Anton Blanchard also from IBM (author and maintainer of Microwatt). Additionally Marius Hillenbrand also from IBM, contributed some extra optimisations and code for s390x (IBM System z mainframes), including optimizations for Z14 CPUs.

There are also some Power9 and Z13 improvements in code base made by Abdelrauf (between 2017-2019), which AFAIK is also from IBM, at least in the past.

There are also some support for Apple Vortex arm cores, by , Martin Kroeker, main maintainer (together with Zhang Xianyi) of OpenBLAS. Martin also added thousands of bugfixes to build system, various compiler support fixes and improvements, and minor optimisations / fixes on many (including POWER9 and POWER10) architectures and in generic code.

[Royi]

Does AMD invest in this project?
It’s their interest to make it as fast as Intel MKL.