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LLVM Clang 12 Merges Support For x86_64 Microarchitecture Levels

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  • LLVM Clang 12 Merges Support For x86_64 Microarchitecture Levels

    Phoronix: LLVM Clang 12 Merges Support For x86_64 Microarchitecture Levels

    In an effort to better cater towards newer and common x86_64 instruction set extensions, open-source toolchain developers are moving ahead with the work on x86_64 micro-architecture feature levels for being able to target a handful of different "levels" beyond the base x86_64 instruction set...

    http://www.phoronix.com/scan.php?pag...croarch-Levels

  • #2
    The biggest grumbling appeared to be around how to handle this:

    x86-64-v4: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL

    This appears to be more streamlined, (I am not a compiler geek) but I am sure someone will find some fault in the breakdown.

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    • #3
      In the future, maybe -v2 can be the default for most distros, though only after a couple of years as C2D is still quite usable (both my parent's computers are C2D-based and surprisingly usable with Xubuntu installed)

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      • #4
        They should add the CPU info of the target to the elf binary or library, then one can possible run "incompatible" binaries via qemu transparently in the same way one can run arm binaries.
        Yes, it will be slower, but at least it will work. This can help programmers who mount the same hdd on different systems.
        A message telling the user they run in "degraded mode" should also help.

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        • #5
          A question for one of the compiler experts around here: These architecture levels can still be used with mtune, right? And what would we miss with march=x86-64-v3 without adding mtune=haswell? I would expect performance oriented distributions to target this level and also set mtune=haswell as even Zen should handle code optimized for Haswell quite well.

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          • #6
            These levels do no favor to pre-Bulldozer AMD CPUs. My 8 year old AMD K10 falls completely through.

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            • #7
              Originally posted by phoronix View Post
              These baselines are laid out via the
              looks like you forgot the rest of the sentence.

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              • #8
                Originally posted by andreano View Post
                These levels do no favor to pre-Bulldozer AMD CPUs. My 8 year old AMD K10 falls completely through.
                As K10 doesn't support crucial instruction sets, I'd say that it is not a surprise at all. Even Sandy/Ivy Bridge only get the v2 level as they both don't support AVX2. I consider this a good sacrifice overall to get manageable baselines for distributions to target. And even v2 is still better off than v1.

                I'd like to see these feature levels trickle over into the Windows world, a version of Windows which is optimized for each feature level would be great (of course they could also cut their support for older generations below v3 but I guess the outcry would be huge).

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                • #9
                  Originally posted by ms178 View Post
                  (of course they could also cut their support for older generations below v3 but I guess the outcry would be huge).
                  Especially from Intel since they even disable avx/2 on some newer chips.

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                  • #10
                    Originally posted by mlau View Post
                    Especially from Intel since they even disable avx/2 on some newer chips.
                    Taking product segmentation to the ISA-level would bite them hard and its customers who bought these chips. But I'd argue rightfully so as it was silly to begin with and when the customers were ignorant of this fact, they need to live with the consequences (as there were options on the market which offered these instructions in the low end).

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