Intel GCC Patches + PRM Update Adds SERIALIZE Instruction, Confirm Atom+Core Hybrid CPUs

[SystemCrasher]

What's wrong is x86 and surroundings + Intel's way of doing things (woeful overengineering, overinclination on way too fast and powerhungry parts + marketing BS). Sure thing, with enough thrust pigs fly just fine. And that thing looks exactly like that.

[polarathene]

big.LITTLE, asshat edition.

What's wrong with it? Should bring more power efficiency so would be great for laptops/portables, could be swung the other way as bringing the market that usually uses atoms as getting some extra processing oomph when needed too.

Dunno if that'd be something useful on laptops that AMD could do too with their 15W or whatever is lowest parts, paired with the higher wattage 45W parts? Since their zen architecture is modular, wouldn't that allow for a mix of power efficient cores and others with more processing grunt?

[SystemCrasher]

Confirm Atom+Core Hybrid CPUs

big.LITTLE, asshat edition.

[jayN]

Are the new instructions the operations needed to enable PCIE5/CXL asymmetric cache coherency, which is expected to be used in Aurora for the GPU shared memory?

[mlau]

This looks like both an instruction and memory barrier at the same time. Might be needed for maximum security... and increased slowness

Yeah, it's an explicit fence and memory barrier, like MIPS's "sync" instruction.

[ldesnogu]

SERIALIZE.
Is that like: "Hey. We can't verify our designs, so here is an instruction to reduce it to i586 speed so you can make sure you don't fall into our fuckups." ?
And also, what is the difference between this and normal memory barriers?

This looks like both an instruction and memory barrier at the same time. Might be needed for maximum security... and increased slowness

[milkylainen]

SERIALIZE.
Is that like: "Hey. We can't verify our designs, so here is an instruction to reduce it to i586 speed so you can make sure you don't fall into our fuckups." ?
And also, what is the difference between this and normal memory barriers?

[phoronix]

Phoronix: Intel GCC Patches + PRM Update Adds SERIALIZE Instruction, Confirm Atom+Core Hybrid CPUs

Intel has seemingly just updated their public programming reference manual as well as sending out some new patches to the GCC compiler for supporting new instructions on yet-to-be-released CPUs...

http://www.phoronix.com/scan.php?page=news_item&px=Intel-PRM-Hybrid-Sapphire