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GNU Assembler Patches Sent Out For Optimizing The Intel Jump Conditional Code Erratum

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  • GNU Assembler Patches Sent Out For Optimizing The Intel Jump Conditional Code Erratum

    Phoronix: GNU Assembler Patches Sent Out For Optimizing The Intel Jump Conditional Code Erratum

    Now that Intel lifted its embargo on the "Jump Conditional Code" erratum affecting Skylake through Cascade Lake processors, while Intel's own Clear Linux was first to carry these patches they have now been sent out on the Binutils mailing list for trying to get the JCC optimization patches into the upstream Binutils/GAS code-base...

    http://www.phoronix.com/scan.php?pag...er-Patches-JCC

  • #2
    the level of Intel bugs and incompetence is hilarious, /me googling availability of AMD Ryzen 3950X ;-) https://www.youtube.com/watch?v=1mkf0O-f4hU

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    • #3
      Is this fix going to affect all code generated from binutils or only with a specific target ?

      Would be sad to make everyone slower just because...

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      • #4
        Originally posted by tchiwam View Post
        Is this fix going to affect all code generated from binutils or only with a specific target ?

        Would be sad to make everyone slower just because...
        The fix seems to be inserting nops(prefixes) to align branches/jumps.

        I don't think it will have any performance impact in general.

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        • #5
          Originally posted by log0 View Post

          The fix seems to be inserting nops(prefixes) to align branches/jumps.

          I don't think it will have any performance impact in general.
          Well it depends how big portion of the code is no-ops. If a significant portion is, then it will unnecessarily occupy room in the cache, slowing down execution.

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          • #6
            I'd still like to see some AMD benchmarks (maybe for older CPU architectures that are still in use today, too?) just to make sure these patches have negligible impact on most use cases.

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            • #7
              Back in 2014 I watched a presentation called "Untrusting the CPU" that had just been given at that year's Chaos Computer Communications-conference and thought to myself that the presenter was just being alarmist about how we should start designing software to assume we can't trust the CPU not to leak critical things like encryption keys. All this would do is add unnecessary complexity and lower performance.

              Well... Turns out he was very much right and I was very much wrong as the issues he brought up were just the tip of the iceberg compared to what was actually out there.

              On top of that further hardware-level exploits like this really do put additional onus on companies like Intel, AMD and ARM to put a lot more effort into thinking about security already on the design level. Intel is obviously the worst offender when it comes to security-related corner cutting by quite a bit, but neither AMD nor ARM are faultless and also need to do better in this regard.

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              • #8
                Originally posted by L_A_G View Post
                Back in 2014 I watched a presentation called "Untrusting the CPU" that had just been given at that year's Chaos Computer Communications-conference and thought to myself that the presenter was just being alarmist about how we should start designing software to assume we can't trust the CPU not to leak critical things like encryption keys. All this would do is add unnecessary complexity and lower performance.
                How does one convey the message to the intended recipient while not trusting interface BUS, RAM, CACHE and CPU... I have a few ideas Anyone interested ?

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                • #9
                  Originally posted by tchiwam View Post
                  How does one convey the message to the intended recipient while not trusting interface BUS, RAM, CACHE and CPU... I have a few ideas Anyone interested ?
                  I mean you can go watch the talk as a video of it is available on their website...

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                  • #10
                    Originally posted by log0 View Post
                    The fix seems to be inserting nops(prefixes) to align branches/jumps.

                    I don't think it will have any performance impact in general.
                    Branches, right? Not branch targets, then? If so, how can you say extra nops won't affect performance?

                    I read elsewhere that Intel estimates up to 4% performance drop.

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