LLVM Adding Support For IBM MASS Library For POWER Vectorization

[phoronix]

Phoronix: LLVM Adding Support For IBM MASS Library For POWER Vectorization

A new addition to the LLVM code-base this week is initial support for IBM's MASS vectorization library...

http://www.phoronix.com/scan.php?page=news_item&px=LLVM-IBM-MASS-Vectorization

[edwaleni]

As Intel pushes more and more vector work into the day to day, it only makes sense that POWER be able to do the same.

per Wikipedia.org:

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Power ISA v2.06 introduces the new VSX vector-scalar instructions^[5] which extend SIMD processing for the Power ISA to support up to 64 registers, with support for regular floating point, decimal floating point and vector execution. POWER7 is the first Power ISA processor to implement Power ISA v2.06.

New instructions are introduced by IBM under the Vector Media Extension category for integer operations as part of the VSX extension in Power ISA 2.07.

New integer vector instructions were introduced by IBM following the VMX encodings as part of the VSX extension in Power ISA v3.0. Shall be introduced with POWER9 processors
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