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Intel: AMD Weak On Battery-Powered Laptop Performance - But DPTF On Linux Still Suck

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  • #21
    Originally posted by Spacefish View Post
    If i just look at the first laptop, for intel it´s a MSI Prestige 14 Evo for AMD it´s a Lenovo Xiaoxin 13
    MSI Prestige 14 Evo (Intel i7) sells for $1,200 @ BestBuy; Lenovo Xiaoxin 13 (Ryzen 7) costs ~$800 (¥ 5,499), and you can get it only in China.

    https://item.lenovo.com.cn/product/1007964.html

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    • #22
      Originally posted by Spacefish View Post

      this is 10th gen (Comet Lake) and NOT 11th gen (Tiger Lake)..
      It still gives an idea what the AMD offerings can do. Don't forget 10th vs 11th difference is not all that much regarding performance.

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      • #23
        Originally posted by DRanged View Post

        It still gives an idea what the AMD offerings can do. Don't forget 10th vs 11th difference is not all that much regarding performance.
        They mainly improved the size of the caches a lot.. Like 2.5x L2 Cache and 50% more L3 Cache (3MB instead of 2MB).
        It will be faster in benchmarks, but won´t compete with Zen 3 IMHO..
        Anyway, today you have the choice between Ice Lake and Renoir and you would probably choose Renoir.. In mid 2021 you will have the choice between Tiger Lake and Cezanne and i would choose Cezanne..

        I don´t see why you would choose a cheaper 8 Core CPU over a more expensive 4 Core CPU with comparable Single Core Performance and Power Draw anyway. Especially as a software dev or creative workload person.. For casual workloads like browsing or office it doesn´t matter anyway / i would choose the cheaper platform.

        One thing i am waiting for: A good 802.11ax Chip with good power efficiency for Laptops from Qualcomm.. Currently Intels AX200 is unmatched IMHO..

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        • #24
          Originally posted by angrypie View Post
          Slow news day? If everything Intel has ever said held any ground we'd be running 10GHz single-core CPUs.
          I'm by no means an Intel fan, but actually Intel did accomplish that goal, at least superficially... Netburst architecture used integer units running at twice the core clock and the core clock got up to the mid-4ghz range, so yeah those integer units got to nearly 10ghz...

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          • #25
            Originally posted by duby229 View Post

            I'm by no means an Intel fan, but actually Intel did accomplish that goal, at least superficially... Netburst architecture used integer units running at twice the core clock and the core clock got up to the mid-4ghz range, so yeah those integer units got to nearly 10ghz...
            The 10GHz thing was called Tejas, and it was supposed to have the whole core at 10GHz, not just a part of it. Netburst's integer units just had double throughput per cycle, much like DDR4 "4000MHz" RAM that runs at 2000MHz effective.

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            • #26
              Originally posted by angrypie View Post

              The 10GHz thing was called Tejas, and it was supposed to have the whole core at 10GHz, not just a part of it. Netburst's integer units just had double throughput per cycle, much like DDR4 "4000MHz" RAM that runs at 2000MHz effective.
              So all types of DDR encode both edges of the clock, hence the name. Intel's Netburst architecture even encode both edges of it's internal busses. Which presents a problem, the buss carries twice the amount of encoding than what an equally clocked integer unit can process. They had an option to either buffer the hell out of the buss or double the clock of the integer units. Buffering the hell out of it would have increased latency too much so they chose to double the clocks....
              http://www.ecs.umass.edu/ece/koren/e...s/Pentium4.pdf

              The processor does ALU operations with an effective latency of one-half of a clock cycle. It does this operation in a sequence of three fast clock cycles (the fast clock runs at 2x the main clock rate) as shown in Figure 7. In the first fast clock cycle, the low order 16-bits are computed and are immediately available to feed the low 16-bits of a dependent operation the very next fast clock cycle. The high-order 16 bits are processed in the next fast cycle, using the carry out just generated by the low 16-bit operation. This upper 16-bit result will be available to the next dependent operation exactly when needed

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              • #27
                Originally posted by Spacefish View Post

                They mainly improved the size of the caches a lot.. Like 2.5x L2 Cache and 50% more L3 Cache (3MB instead of 2MB).
                It will be faster in benchmarks, but won´t compete with Zen 3 IMHO..
                Anyway, today you have the choice between Ice Lake and Renoir and you would probably choose Renoir.. In mid 2021 you will have the choice between Tiger Lake and Cezanne and i would choose Cezanne..

                I don´t see why you would choose a cheaper 8 Core CPU over a more expensive 4 Core CPU with comparable Single Core Performance and Power Draw anyway. Especially as a software dev or creative workload person.. For casual workloads like browsing or office it doesn´t matter anyway / i would choose the cheaper platform.

                One thing i am waiting for: A good 802.11ax Chip with good power efficiency for Laptops from Qualcomm.. Currently Intels AX200 is unmatched IMHO..
                Where did I say I was going for either one. I've got a Lenovo Legion y520 Intel i7 gtx1050 16GB ram bought in summer 2016 and that one will suffice for a couple years more. Works great with Debian testing and wine-staging for games, same goes for Windows 10 and gaming (dual boot when needed).

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                • #28
                  Am I the only one who picked up on the use of a now-socially-unacceptable term, by no less than the esteemed owner of this website? To wit:

                  "Intel: AMD Gimps On Battery-Powered Laptop Performance..."

                  "...to basically plead their case that AMD Ryzen laptops are gimping on battery-powered performance..."

                  If I'm not mistaken, "gimp" is one of those words which is now verboten, thanks to the brain-dead, mouth-breathing, room-temperature-IQ SJWs.

                  From the holder of a MASTER'S DEGREE, who is a MASTER ELECTRICIAN, and who teaches MASTER-SLAVE flip-flops in a logic design course...and who will never cave in to all you pathetic, social-justice-seeking queerdos and LBJQMNORST...effetes who have no real work to do, except to agitate; and tell the rest of us how you THINK we should act. For all of you, I have a parting, sincere, heartfelt suggestion: fuck you, AND your agendas.

                  And find a real job. If you had to be at work at 8 in the morning, you wouldn't have time for the shit you spread.


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                  • #29
                    Originally posted by duby229 View Post
                    So all types of DDR encode both edges of the clock, hence the name. Intel's Netburst architecture even encode both edges of it's internal busses. Which presents a problem, the buss carries twice the amount of encoding than what an equally clocked integer unit can process. They had an option to either buffer the hell out of the buss or double the clock of the integer units. Buffering the hell out of it would have increased latency too much so they chose to double the clocks....
                    http://www.ecs.umass.edu/ece/koren/e...s/Pentium4.pdf
                    It's been a few years and I didn't quite remember the details of their implementation, but that's indeed very elegant for Intel. Too bad it didn't amount to anything because the P4 was eaten alive by the Athlon.

                    Seems like the days of "speed demons" are over though. Wide cores are the future.

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                    • #30
                      Originally posted by angrypie View Post

                      It's been a few years and I didn't quite remember the details of their implementation, but that's indeed very elegant for Intel. Too bad it didn't amount to anything because the P4 was eaten alive by the Athlon.

                      Seems like the days of "speed demons" are over though. Wide cores are the future.
                      Yeah it did, Athlon Thunderbird and up had three integer units per core and had a really sophisticated fast path. P4 had two integer units per core and could only put a very limited subset of x86 on the fast path. Athlon could put far more code on the fast path than P4 could.

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