Originally posted by the_scx
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Originally posted by the_scx
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The biggest barrier is the software stack. Followed by lack of parties interested to invest the money to make risc-v work at the high end nm. This is why arm position is not as solid as it first sounds. There is a unrestricted alternative that can perform very well.
Originally posted by the_scx
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Here is a horrible question how fast is Adreno 640 when its doing FP64 that right it does not support that. This risc-v gpu design is a 64FP and 64bit Integer design. That 5-6 GFLOPs on a single processing core of a GPU is not bad once you 1 wake up its only a single processing core 2 its old nm and it is FP64.
Adreno 405 is what you would have to compare that risc-v prototype against and then allow that this has more silicon are and cores and is only FP32.
Big thing about this first chip is to provide the RISC-V graphics ISA with a test platform to develop drivers against and validate the ISA design. Once that is done how fast it can be scaled up will be a interesting question mostly likely totally limited by budget/investment.
Originally posted by the_scx
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Did you miss that Arm and Risc-v can use compatible busses. The question is being answered very carefully because that chip was not just arm its arm/risc-v hybrid.
Risc-v is something interesting in this regard with arm it does not have to be all or nothing. Yes it possible to do like arm big/little but instead arm be big and risc-v be the little or reversed. This makes that basestation chip of Huawei very interesting.
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