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The Performance & Power Improvement Of Steam Deck OLED's 6nm APU

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  • scineram
    replied
    Originally posted by drakonas777 View Post
    Show the list of removed stuff and die space they took.
    I just told you some of what is known, retard.

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  • catpig
    replied
    Originally posted by jayN View Post
    Interesting, cheers

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  • drakonas777
    replied
    Show the list of removed stuff and die space they took.

    Leave a comment:


  • scineram
    replied
    Originally posted by drakonas777 View Post
    Physical dimensions of a N6 transistors are irrelevant for this discussion. The fact is N6 offers 17-25% better density than N7/P and that is the only reason why SoC of OLED version is smaller. HW IP blocks have not changed, GPU/CPU core config has not changed, I/O has not changed. "AMD did something unknown in SoC design to make it smaller" is a total bullshit.

    Lithography is a king. It was always the case it will be always the case.
    Total bullshit. It doesn't shrink anywhere near that, especially SRAM does fuck all. They removed a bunch of crap that was just unused, like the Cadense DSPs.

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  • Anux
    replied
    Originally posted by jayN View Post
    am I allowed to post this link?
    Yes looks like you can. Thanks, I haven't read this before, some nice details in there.

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  • drakonas777
    replied
    Physical dimensions of a N6 transistors are irrelevant for this discussion. The fact is N6 offers 17-25% better density than N7/P and that is the only reason why SoC of OLED version is smaller. HW IP blocks have not changed, GPU/CPU core config has not changed, I/O has not changed. "AMD did something unknown in SoC design to make it smaller" is a total bullshit.

    Lithography is a king. It was always the case it will be always the case.

    Leave a comment:


  • jayN
    replied
    am I allowed to post this link?
    An update on TSMC's upcoming 5-nanometer process technology.

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  • jayN
    replied
    I recall N7 and N6 have the same design rules ... just replaces DUV with EUV on a few layers. Not really considered a shrink. TSM just likes to lower that number and keep you guessing. This was from old articles on fuse.

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  • catpig
    replied
    Originally posted by Mathias View Post
    What makes you think Deck LCD uses N7+ Process? I did a quick search and found N7+ was supposed to be used from Zen3, so Zen2 should use normal N7 process. So going to N6 should result in 12% more density.
    I didn't say that, sorry if it looked like I was implying it. I was just saying that the "nm" marketing labels don't refer to any physical size nor density, as the table on wiki illustrates by showing "7nm" N7+ having virtually identical density to "6nm" N6.
    Also, AMD uses different processes for the same core type all the time - e.g. according to https://www.anandtech.com/show/17584...dna-2-graphics the "normal" Zen2 APUs used "6nm".
    Whilst the original deck is a semi-custom Zen2 APU, yet it used some form of "7nm". The new deck still uses Zen2, but is "6nm". There's many ways to optimise area usage other than making individual transistor parts smaller, and that's what N6 and/or additional work put in by AMD did here.

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  • catpig
    replied
    Originally posted by Anux View Post
    But don't we agree that they only made it smaller here?


    I would say it's the same with some error tolerance. But if they are running the same frequencies with the same voltages it is to be expected.
    I meant individual transistors/transistor parts. I'd say the benchmark difference is a bit large to call it error tolerance, but you're quite right that that alone does not plausibly justify the cost of doing all the necessary changes.
    And yeah, it being cheaper probably is the reason, or at least a reason. Though I can think of two more plausible reasons: switching to the new process reduces load on the chip factories, allowing larger volume of chips coming out. Assuming AMD makes a profit on each chip (and why else would they agree to keep making it) that would still be a benefit, as it allows them to either make more chips for the deck, or more chips for other markets. The reduced area usage might also have been useful in allowing the larger battery and/or shorter traces to memory etc. But I'll pre-emptively concede that I'm starting to stretch "plausible reason" with that last sentence

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