Coreboot Lands More RISC-V / lowRISC Code

[phoronix]

Phoronix: Coreboot Lands More RISC-V / lowRISC Code

As some early post-Coreboot 4.5 changes are some work to benefit fans of the RISC-V ISA...

http://www.phoronix.com/scan.php?page=news_item&px=Coreboot-RISC-V-Low-Better

[microcode]

Very promising, I wonder how long until consumer electronics are shipping RISC-V in the tens of millions of cores per month.

[uid313]

Does LLVM support RISC-V?
There is a GCC version with RISC-V support, but will it be mainlined?

[M@yeulC]

Interesting, but was there any reason why Plan 9 was chosen instead of another OS? I am just curious... This isn't a very common choice.

microcode, I would very much like to see that happening, although I hope vendors won't integrate backdoors/security holes in it... I wish it was GPL-licensed.

[pal666]

Does LLVM support RISC-V?
There is a GCC version with RISC-V support, but will it be mainlined?

yes yes

[andresdju]

Interesting, but was there any reason why Plan 9 was chosen instead of another OS? I am just curious... This isn't a very common choice.

Ron Minnich is founder of coreboot (before LinuxBIOS) and involved in Plan9 (and now Harvey) for decades. He is now working on risc-v coreboot port and risc-v Harvey port, so trying to boot Plan9 kernel with coreboot on risc-v seems very natural.

[M@yeulC]

Ron Minnich is founder of coreboot (before LinuxBIOS) and involved in Plan9 (and now Harvey) for decades. He is now working on risc-v coreboot port and risc-v Harvey port, so trying to boot Plan9 kernel with coreboot on risc-v seems very natural.

Thanks for the explanation This seems very natural indeed.

[stiiixy]

Work with what you know, ay.