GCC 11's x86-64 Microarchitecture Feature Levels Are Ready To Roll

[Paradigm Shifter]

I read somewhere the hammer comes down on Zen 4.

Where? I hope so. AVX-512 is just about the only reason I even think about Intel silicon for new purchases.

[zxy_thf]

I wish they'd have added a level for Sandybridge, since AVX is a pretty big deal. My employer is still supporting customers with Sandybridge systems (these are appliances with a long service life) and my primary home machines are that generation.

v4 seems like a hammer for pushing AMD to support AVX-512.

Meanwhile, v3 is a hammer to tell Intel stop messing with their Pentium and Celeron lines.

[smitty3268]

Where? I hope so. AVX-512 is just about the only reason I even think about Intel silicon for new purchases.

It's just a rumor at the moment, but it makes sense for a lot of reasons.

They'll have more die space to add features after a node shrink, and AVX-512 is going to be one of the things a lot of people will start asking for vs other new instructions. Plus Intel will have started including it in more of their desktop processors by then - for now, many still don't have it as I believe it's been relegated to their 10nm laptop chips, server chips, and some high end enthusiast desktop chips, but in a few years it will be a lot more common.

There will apparently (again, rumored) be a Zen 3 refresh out first, though, so it may be a bit longer for Zen 4 to appear. If AVX-512 is important you may not want to wait that long.

[Paradigm Shifter]

It's just a rumor at the moment, but it makes sense for a lot of reasons.

They'll have more die space to add features after a node shrink, and AVX-512 is going to be one of the things a lot of people will start asking for vs other new instructions. Plus Intel will have started including it in more of their desktop processors by then - for now, many still don't have it as I believe it's been relegated to their 10nm laptop chips, server chips, and some high end enthusiast desktop chips, but in a few years it will be a lot more common.

There will apparently (again, rumored) be a Zen 3 refresh out first, though, so it may be a bit longer for Zen 4 to appear. If AVX-512 is important you may not want to wait that long.

OK, thanks mate. I've seen similar rumours, largely on places I don't trust to be accurate, so was hoping you'd got a better source. No worries.

AVX-512 isn't essential, it's just one option to become less dependent on CUDA. With the exception of motherboard RAID, I'd rather buy AMD than Intel, but since I now need to start seriously looking at systems capable of 1TB(+) RAM, going AVX-512 Intel isn't that much more expensive if I can source the Xeon Gold-rebranded Xeon Platinum chips.

[pal666]

i wonder why amd architectures are defined in terms of nehalem and haswell

[smitty3268]

OK, thanks mate. I've seen similar rumours, largely on places I don't trust to be accurate, so was hoping you'd got a better source. No worries.

I think the only really solid info we have on Zen 4 at the moment is that it will be a newer TSMC process (obviously), have a new socket, and add DDR5 support. I'd rank AVX-512 up there as almost a lock, personally, though, but we'll see.

[CochainComplex]

I think the only really solid info we have on Zen 4 at the moment is that it will be a newer TSMC process (obviously), have a new socket, and add DDR5 support. I'd rank AVX-512 up there as almost a lock, personally, though, but we'll see.

I can recommend AdoredTV on youtube. Maybe he got some likely scenarios covered. His predictions usually are not so far fetched.

[milkylainen]

Seems like compilers are in need of a --do-a-best-guess-of-flags-to-this-cpu
It's going to be a mess.

[coder]

Meanwhile, v3 is a hammer to tell Intel stop messing with their Pentium and Celeron lines.

Why?

Not all instructions need direct use within application code, to be useful. For example, Inel's TSX can provide measurable benefits, simply by optimizing locking code in platform libs, like libc and libpthread. Or take crypto extensions, which only need to be harnessed within a similarly small subset of libraries. Or cache control instructions, that just need adoption within a few key parts of the kernel. Look inside some of libc's string functions, and you'll find hand-coded AVX2 paths lurking. Even AI instructions need only be used within a few popular AI frameworks to realize their potential.

Of course, optimized libraries aren't enough to fully exploit every instruction set extension, but a lot of the targeted extensions Intel has been putting in their "Atom" cores fall in that category.

[RubenKelevra]

Kinda weird to make the cut at AVX2. There are a lot of AVX processors out there which cannot use the 2 times faster SSE4.x instructions AVX offers.