Linux 5.10 Scheduler Updates Bring SMT Balancing Tweaks

[phoronix]

Phoronix: Linux 5.10 Scheduler Updates Bring SMT Balancing Tweaks

Ingo Molnar as usual is quite quick in submitting his changes for the new kernel merge window in the areas he oversees. With the scheduler changes for Linux 5.10 there are some changes worth mentioning...

http://www.phoronix.com/scan.php?page=news_item&px=Linux-5.10-Scheduler-Changes

[FireBurn]

Does cache hotness not matter when migrating between core complexes (CCX) that don't share L3 cache? I'm thinking specifically about Ryzen chips

[milkylainen]

"- Cache hotness is now ignored for SMT migration since they share the same core and in turn the same caches."

Umm. In the general scheduler or what? Would not that depend very much on what the actual CPU implementation looks like?

[jrdoane]

"- Cache hotness is now ignored for SMT migration since they share the same core and in turn the same caches."

Umm. In the general scheduler or what? Would not that depend very much on what the actual CPU implementation looks like?

SMT implies concurrently executing multiple threads against a single execution core. Regardless of CPU implementation, it's going to be in the same core. If it's not the same core, it's another core, not SMT.

[smitty3268]

Does cache hotness not matter when migrating between core complexes (CCX) that don't share L3 cache? I'm thinking specifically about Ryzen chips

It does. It also matters when switching to another core on the same L3 cache, because it will still have different L1 and L2 caches.

It's only when using SMT on the same core that it can be ignored.

[milkylainen]

SMT implies concurrently executing multiple threads against a single execution core. Regardless of CPU implementation, it's going to be in the same core. If it's not the same core, it's another core, not SMT.

The question wasn't if they execute on partially some shared resources, like ex. That's the obvious answer.
The question is if you can guarantee that the CPU architecture implies that you reach the same memory subsystem channel if executing another context on the same execution unit. I can agree that such an architecture would probably not be called SMT, hence not a problem, but still think it is a very blunt assumption to make.

[droste]

The question wasn't if they execute on partially some shared resources, like ex. That's the obvious answer.
The question is if you can guarantee that the CPU architecture implies that you reach the same memory subsystem channel if executing another context on the same execution unit. I can agree that such an architecture would probably not be called SMT, hence not a problem, but still think it is a very blunt assumption to make.

I think you're right, but if the cache isn't shared on the same core, how big is the chance you find another core that shares the cache?
That would be a weird design :-D
Staying on the same core is probably still the best bet.