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Linux 5.5 To Enable Intel's 5-Level Paging Support By Default

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  • Linux 5.5 To Enable Intel's 5-Level Paging Support By Default

    Phoronix: Linux 5.5 To Enable Intel's 5-Level Paging Support By Default

    For several release cycles already the Linux kernel has supported Intel's 5-level paging for increasing the virtual and physical address space available to systems while for Linux 5.5 the five-level support is being enabled by default...

    http://www.phoronix.com/scan.php?pag...5-Level-Paging

  • #2
    So, this will not have any performance penalty after all?

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    • #3
      Originally posted by caligula View Post
      So, this will not have any performance penalty after all?
      They should be addressed, but we'll see soon enough how 4-level paging hardware does with the new kernel.
      Michael Larabel
      http://www.michaellarabel.com/

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      • #4
        Originally posted by Michael View Post

        They should be addressed, but we'll see soon enough how 4-level paging hardware does with the new kernel.
        Maybe I'm missing something, but doesn't each level of paging involve another level of indirection - that is, more computational work?

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        • #5
          Maybe for some big companies or even governmental systems might need this but as a user, I am still waiting: an in kernel ipc ( kdbus born as dead, bus1 forgotten,... )

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          • #6
            Originally posted by caligula View Post

            Maybe I'm missing something, but doesn't each level of paging involve another level of indirection - that is, more computational work?
            Yes, and presumably that's where the performance regressions come from. The pull request Michael links to just enables the option by default, the actual work to address the performance issues are elsewhere, and I'm too lazy to look it up. But just speculating, there's two cases to consider:

            1) Running on hw with 4-level page tables. So how can the code be written so there's no, or at least minimal, performance impact from being able to support 5-level page tables when the hw isn't there? If nothing else, can probably have some boot-time code modification to select the correct path to use like is already done for a lot of other things?

            2) Running on hw with 5-level page tables but not having enough physical memory installed to really need it. Slightly trickier, but maybe making sure that virtual memory is laid out such that the topmost 5th level page table entry is always constant and thus in the TLB?

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            • #7
              Originally posted by caligula View Post

              Maybe I'm missing something, but doesn't each level of paging involve another level of indirection - that is, more computational work?
              Paging functionality pretty much has to be hardware accelerated with specific silicon on a CPU to be usable at modern computation speeds. In that context, as long as the hardware is meant to process 5 level tables, it should be as fast as a 4 level.

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