ThunderX2 Getting Big MEMMOVE Performance Boost With Glibc 2.30

[RussianNeuroMancer]

Can you order from UK? If so, then have a look at avantek: https://store.avantek.co.uk/arm-desktops.html

I can, but with 30% import tax for parcels with cost above 500 EUR it's just not much cheaper than cheapest Huawei server, but much worse performance wise. Maybe there is ATX or ITX board with modern ARM SoC? This way it would be cheaper to order board and buy PSU and case locally.

[milkylainen]

the ISA might be generic - but the rest of the chip may not be. There could be all sorts of constraints on how memory is moved around (slow/weak/cheap interconnects).

Then please explain the announcement?
"This optimization comes by using SIMD load/stores rather than GPRs for large overlapping forward moves."
I'm pretty sure whatever optimizations they are providing would benefit other SoCs on the same AArch64 v8.x+
All AArch64 SoCs that I know of have hardware prefetchers for data. They will gladly follow a linear access pattern without any issues.

[boxie]

Then please explain the announcement?
"This optimization comes by using SIMD load/stores rather than GPRs for large overlapping forward moves."
I'm pretty sure whatever optimizations they are providing would benefit other SoCs on the same AArch64 v8.x+
All AArch64 SoCs that I know of have hardware prefetchers for data. They will gladly follow a linear access pattern without any issues.

Sure - this might apply to other SoCs, but also may not. This optimisations seems to be aimed at the SoC architecture (the way the engineers implemented things) rather than at an Instruction Set level.