Thunderbolt Is Seeing A Lot Of Improvements For Linux 5.2

[nils_]

I'm fairly certain the next iteration will be named USB 3.3 x2 +3 TurboSpeed v2. Once it's released, they will retroactively rename the previous versions of course. But to avoid consumer confusion, they will use the marketing names SuperSpeed, UltraSpeed, MegaSpeed, and SpeedySpeed to differentiate them.

Also a new Type-Ca cable is in the work that is non-reversible to restore the classic user experience of the 3xflip'n'plug™

[starshipeleven]

They'll get to that in due time my good man

Yes but it won't matter just as it didn't with USB 3.0 revisions.

99.99% of current USB 3.0 devices aren't using controllers of a higher revision than the bare minimum needed to be USB 3.0 (aka 5Gbit/s), and even if they did it's irrelevant as most USB 3.0 host ports are still not really 10Gbit/s anyway.

[starshipeleven]

Also a new Type-Ca cable is in the work that is non-reversible to restore the classic user experience of the 3xflip'n'plug™

[nils_]

Yes but it won't matter just as it didn't with USB 3.0 revisions.

99.99% of current USB 3.0 devices aren't using controllers of a higher revision than the bare minimum needed to be USB 3.0 (aka 5Gbit/s), and even if they did it's irrelevant as most USB 3.0 host ports are still not really 10Gbit/s anyway.

And then of course many CPUs don't have the PCIe/DMI lanes to support a larger number of ports (or even more than one).

[starshipeleven]

And then of course many CPUs don't have the PCIe/DMI lanes to support a larger number of ports (or even more than one).

Yes, that's one of the main reasons USB 3.0 didn't go much beyond the first gen in real life.

Even with PCIe 5.0 lanes ( 4Gbit/s bidirectional) you would still need like 10 lanes to provide a single 40Gbit/s link for USB4.
With PCIe 4.0 you would need 20, and so on, doubling for each PCIe revision you decrease.
This is just silly, even on a tower PC.

These high-speed interfaces will get any traction once they are integrated in the main CPU die, just like PCIe, RAM and whatever else controllers.
There you don't have bandwith issues as the controller will be on the on-die interconnect bus.

[nils_]

Even with PCIe 5.0 lanes ( 4Gbit/s bidirectional) you would still need like 10 lanes to provide a single 40Gbit/s link for USB4.
With PCIe 4.0 you would need 20, and so on, doubling for each PCIe revision you decrease.
This is just silly, even on a tower PC.

You're mixing up bits and bytes there, PCIe 5.0 can do (almost) 4 GiB per second, so almost 35Gbit/s. Though 40Gbit/s is less than what Intel provides in their connect to the PCH (I believe it's currently 4 Lanes of DMI which is similar to 4 PCIe 3 lanes).