Originally posted by coder
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AHCI is not NVME. NVME is diffrent protocol to AHCI, and requires hardware support. You won't be able to use NVME drive in NVME way if you don't have required hardware for it. Haswell refresh is minimum required hardware to suppport NVMe. and NVMe specifies a communication SSD <-> CPU (or chipset) and it has special hardware inside to accelerate operating on such protocols. And this is why you will have performance penalty because even if you get top of the line SSD it won't be able to communicate in NVME mode, and that will hurt stuff like IOPS a lot.
it is not imaginary thing dropouts, I seen LinusTechTips as well Level1 techs talking about it in few cases when it was limited.. When in normal way of working such platform rarerly hits such limits like QPI links, they do exist and when designing a workload that will scale well to 4P you can do that. Why do you think super computers go for Mellanox etc. and Intel all the time was upgrading QPI and UPI with way bigger speeds then QPI links - that is right because it is needed for them. Now for most workloads it won't happen, but you could imagine easly a case when CPU 2 is talking to GPU connected to CPU1, at the same time CPU1 wants something from RAM of CPU2, and viola you pretty much put maximum limit on QPI link cpu1 <-> cpu2. This is why server or multinode software puts such a heavy task of making sure algorithms are NUMA aware, and this is why (again not suprising) best scalability you achieve on openssl or NAS performance benchmark or NAMD - those were literally designed to. But typical render engine sometimes needs to load something from RAM of another CPU and that slows it down, that is why you achieve still good scallability but not close to 100% like 3 ones i mentioned.
If you claim such IDEs are bad, then sorry that industry standard InteliJ, Visual studio, all will have a minor hiccup there and there. And when you debug something you mostly will debug one part of it and again single threaded performance wins.
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