FreeBSD Kernel Patch Posted For Addressing Ryzen Errata

[phoronix]

Phoronix: FreeBSD Kernel Patch Posted For Addressing Ryzen Errata

A few days back I wrote about workarounds for getting FreeBSD running stable on AMD Ryzen via a script to adjust some of the CPU's MSRs based upon a recently-updated AMD revision guide. That script, which was making use of FreeBSD's cpucontrol utility for adjusting the bits, has now morphed into a kernel patch...

http://www.phoronix.com/scan.php?page=news_item&px=FreeBSD-Ryzen-Errata-Kernel

[PluMGMK]

I can't believe it took this long…

[aht0]

I can't believe it took this long…

.. based upon a recently-updated AMD revision guide

umm.. ?

[rene]

There was also a time when CPUs just worked™, and I'm even mostly eying Intel here, ... maybe RISC would have been the more sustainable choice after all? https://www.youtube.com/watch?v=LMSIng6v-LU ;-)

[PluMGMK]

umm.. ?

I obviously meant that I can't believe it took *AMD* this long to figure out what was wrong. FreeBSD guys are doing a bang-up job!

[tiwake]

There was also a time when CPUs just worked™, and I'm even mostly eying Intel here, ... maybe RISC would have been the more sustainable choice after all? https://www.youtube.com/watch?v=LMSIng6v-LU ;-)

It would not surprise me at all if the issue with runtimes being all over the place is because its difficult to optimize CISC compilers, even though they dominate the market. I would expect optimizing a compiler would be easier for RISC-based instructions.

[starshipeleven]

There was also a time when CPUs just worked™, and I'm even mostly eying Intel here, ... maybe RISC would have been the more sustainable choice after all? https://www.youtube.com/watch?v=LMSIng6v-LU ;-)

It was also the time when they weren't anywhere near as complex as now. I remember volumes of errata for Intel stuff down to the stone age of CPUs.

While I'm with you with RISC, I don't think it would solve the problem, just lessen it.

[k1e0x]

There was also a time when CPUs just worked™, and I'm even mostly eying Intel here, ... maybe RISC would have been the more sustainable choice after all? https://www.youtube.com/watch?v=LMSIng6v-LU ;-)

When was this? Before Cyrix?

[rene]

It was also the time when they weren't anywhere near as complex as now. I remember volumes of errata for Intel stuff down to the stone age of CPUs.

While I'm with you with RISC, I don't think it would solve the problem, just lessen it.

there is at least one formally verified risvc core ;-) Also maybe we should take some more drastic steps in simplifying CPUs and doing more in fixable software. E.g the Transmeta idea was not too bad, this LVIW had some pretty cool register write buffer and rollback to do all the protected mode abstraction in the code morphing software. Maybe RISC-like with some hardware assisted shadow register rollback glue for software assisted virtualization would be pretty interesting. Less silicon, more software to improve and fix. Imaging we could exploit such an CPU like the Transmeta one and write our own PowerPC or RISCV ISA code morphing ;-) PS: if someone wants to leak vintage TM CMS source to me for tinkering, I got both a Crusoe and Efficeon ;-)

[rene]

When was this? Before Cyrix?

What have Cyrix "clones" to do with Intel though? My am386dx40 is still running quite fine tough: https://www.youtube.com/watch?v=afwIZDtrRj4 but well, maybe with all the esoteric extensions that Intel hacks onto the aging 8086 ISA things became a little bit unmanageable Spaghetti, ... and many of the extensions are not even used often.