AMD 4th Gen EPYC 9654 "Genoa" AVX-512 Performance Analysis

[Anux]

MCD stands for "Memory Cache Die". Those chiplets are mostly SRAM + some I/O.

Nahh, I meant chiplets in general.

On the topic of SRAM density vs logic density, here is a useful tidbit: https://electronics.stackexchange.co...o-random-logic

That 222 M per mm² is a single cell designed for highest density. But it's missing a way to access it if you surround it with other cells (address logic and wires, as well as data wires). And it won't work in a 6 GHz CPU.

Why would AMD put it's cache on a 6nm chiplet and the compute on a 5nm chiplet if memory was denser than compute?

[nicalandia]

First look at what Intel Sapphire Rapids Performance under Linux Looks, So far it's only the 32 Core CPU model(8462Y in 2S)

Here is vs 2S Genoa 9374F and 1P 7773X

image.png

https://openbenchmarking.org/result/...NE-BCMRKLOG658


Wayback Machine Snapshot of the webiste before it was taken down

https://web.archive.org/web/20221221002636/https://openbenchmarking.org/result/2212207-NE-BCMRKLOG658,2211147-PTS-EPYC937413