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Intel Linear Address Masking "LAM" Ready For Linux 6.2

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  • Intel Linear Address Masking "LAM" Ready For Linux 6.2

    Phoronix: Intel Linear Address Masking "LAM" Ready For Linux 6.2

    Going back to late 2020 Intel's open-source/Linux engineers have been working on Linear Address Masking "LAM" enablement for that feature coming with future processors. With the upcoming Linux 6.2, the kernel-side enablement for Intel LAM appears to be finally wrapped up...

    https://www.phoronix.com/news/Intel-LAM-Linux-6.2

  • #2
    Typo:

    "The Intel LAN kernel patches"

    Should be Intel LAM.

    Which intel processor families support this Intel Lam?


    ​​​​​​

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    • #3
      Originally posted by bezirg View Post
      Typo:

      "The Intel LAN kernel patches"

      Should be Intel LAM.

      Which intel processor families support this Intel Lam?


      ​​​​​​
      Thanks.

      As mentioned in the article, I haven't seen Intel explicitly state supported processors/plans -- unless it was quietly done elsewhere that I haven't noticed. The programming reference manual continues to just say "future processors"
      Michael Larabel
      https://www.michaellarabel.com/

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      • #4
        Originally posted by Michael View Post

        Thanks.

        As mentioned in the article, I haven't seen Intel explicitly state supported processors/plans -- unless it was quietly done elsewhere that I haven't noticed. The programming reference manual continues to just say "future processors"
        I see ithis code n the aforementioned patch. Unfortunately I am not verse in the cpuid_count intrinsic and I don't have some new intel system to test it out.

        ```
        static inline int cpu_has_lam(void)
        {
        unsigned int cpuinfo[4];

        __cpuid_count(0x7, 1, cpuinfo[0], cpuinfo[1], cpuinfo[2], cpuinfo[3]);

        return (cpuinfo[0] & (1 << 26));
        }
        ​```
        Last edited by bezirg; 14 November 2022, 08:03 AM.

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        • #5
          So Intel's on the LAM



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          • #6
            Seems nice but the kind of thing that would have made sense to pursue a decade ago, back when memory was more limited and people needed more convincing to upgrade to a 64 bit OS.

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            • #7
              So... exactly what does this? If I understand it right, it just means that you can say to the processor "hey, I will use only the X lower bits of the pointers, and the upper bits will be flags, so ignore them when I use a pointer". Is that?

              Because if that is the case, I would have accepted that up to 1990, but not in 2022...

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              • #8
                The presentation does a terrible job at selling this. It's a ton of work for something that has an easy software alternative - which could be accelerated via instruction fusion. Where is the massive upside that justifies this?

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                • #9
                  Sounds to me like they want to catch up with what Arm has with the "TBI" (top byte ignore) and later "MTE" (memory tagging extension), which is handy for bringing memory footprint with things like (K)ASAN down.

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