And when will https://www.crowdsupply.com/eoma68/micro-desktop be done? We're close to 5ys on that one now.
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Libre-SOC Test ASIC Going To Fabrication, Using TSMC 180nm Process
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Originally posted by libv View PostAnd when will https://www.crowdsupply.com/eoma68/micro-desktop be done? We're close to 5ys on that one now.
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I still struggle with a relatively simple systems like https://eater.net/8bit/ . I would love to spend some time to learn how both nmigen and this SoC works.
Not having signed a foundry NDA is a huge deal! Hope you reach 300 mhz (fingers crossed)!
Well done to everyone involved, especially Luke (with the early development woes).
PS: I'm still sad that the RISC-V route did not work out. Sorry if I'm rubbing salt in the wound. Not trying to start a war just thinking utopian style.
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Originally posted by Jabberwocky View PostI still struggle with a relatively simple systems like https://eater.net/8bit/ . I would love to spend some time to learn how both nmigen and this SoC works.
Not having signed a foundry NDA is a huge deal! Hope you reach 300 mhz (fingers crossed)!
Well done to everyone involved, especially Luke (with the early development woes).
PS: I'm still sad that the RISC-V route did not work out. Sorry if I'm rubbing salt in the wound. Not trying to start a war just thinking utopian style.
the clue from adrian_b's post is:
RISC-V is however a special case. Even if I have never spent time with implementing any program for it, after having experience with assembly programming for more than a dozen ISAs, when I see that almost any RISC-V loop may require up to a double number of instructions compared to most other ISAs...
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Originally posted by Jabberwocky View PostPS: I'm still sad that the RISC-V route did not work out. Sorry if I'm rubbing salt in the wound. Not trying to start a war just thinking utopian style.
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Originally posted by lkcl View Post
well then you could start here https://libre-soc.org/3d_gpu/tutorial/ and it's just a matter of being patient and going through things. i strongly recommend using the yosys "show" command because you get a 2D visual graph version of what is is you actually created. i found that's incredibly important to understanding.
i'll be happy if we achieve 25
appreciated. it's been tough on everyone.
don't be. it turns out we dodged a major bullet there - here's some technical details by adrian_b. https://news.ycombinator.com/item?id=24459314
the clue from adrian_b's post is:
i go into a bit more detail here: https://youtu.be/kVT31txMBQo?t=282
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Originally posted by programmerjake View Postand by having well-defined subsets that compose well, with RV32I probably being the best ISA I've seen so far for a super-tiny embedded cpu), though I am pretty disappointed by their organizational mistakes and the attitude of some of their leaders...oh well.
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Originally posted by monty11ez View Post
I see nmigen is being used instead of verilog, but why not VHDL?
1. vhdl didn't have good open-source synthesis support when we started (ghdl was simulate-only).
2. python has nicer meta-programming features (generating HDL ASTs using algorithms, think like C++'s template meta-programming, but more powerful and easier to understand) -- it's just more python.
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Originally posted by monty11ez View Post
I see nmigen is being used instead of verilog, but why not VHDL?
quite simple really (what jacob said, above)
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Originally posted by lkcl View Post
VHDL cannot do object-orientated multiple inheritance HDL, cannot do classes at all, is not 3rd on the TIOBE index and is not known by 30% of the world's programmers.
quite simple really (what jacob said, above)
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