Announcement

Collapse
No announcement yet.

CISC vs RISC

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • #21
    Originally posted by duby229 View Post
    OMFG!!!

    DUMBASS! That part you quoted isn't talking about micro-ops! It's talking about instructions! RISC instructions get decoded into direct 1 to 1 micro-ops! When x86 transitioned to a RISC microarchitecture, it too has to decode instructions into direct 1 to 1 micro-ops. That is what it was talking about!

    The part you didn't bold is that part that explains it!!!
    How the fuck does x86 decode instructions into direct 1 to 1 micro-ops? What's the fucking point then?

    And also, how the FUCK does direct 1-to-1 translation have ANYTHING to do with fusion which is 2-to-1 you dumbass clown?

    Fusion = 2-to-1. You get TWO instructions at the app level (in RAM etc), converted into ONE micro-op.

    Originally posted by duby229 View Post
    Simpler does not mean smaller. Simpler means that these instructions are compiled into a single micro-op which functions totally independently and on its own and they are much bigger than microcodes used to be Simpler is achieved by splitting these tasks up into stages where the instruction can flow from one stage to the next.

    EDIT: The fact that ancient RISC architectures used to use simple instructions for their ISAs doesn't change the fact that x86 and ARM and PPC all do exactly the same thing but with much more complex instructions.

    Transistor budget is astounding today, it makes total sense that architectures have become more complex and so we can DO MORE today than we used to! I wonder why you can't figure that out?
    What's "simpler" about a micro-op that compares and jumps, compared to an instruction that just compares, and one that just jumps?

    2-to-1 moron. That's what fusion is.

    Get the fuck over it. Fusion is CISC. Micro ops are both CISC and RISC, they're not "RISC internally". Delusional dumbass.

    Comment


    • #22
      Originally posted by Weasel View Post
      How the fuck does x86 decode instructions into direct 1 to 1 micro-ops? What's the fucking point then?

      And also, how the FUCK does direct 1-to-1 translation have ANYTHING to do with fusion which is 2-to-1 you dumbass clown?

      Fusion = 2-to-1. You get TWO instructions at the app level (in RAM etc), converted into ONE micro-op.

      What's "simpler" about a micro-op that compares and jumps, compared to an instruction that just compares, and one that just jumps?

      2-to-1 moron. That's what fusion is.

      Get the fuck over it. Fusion is CISC. Micro ops are both CISC and RISC, they're not "RISC internally". Delusional dumbass.
      IT'S AN EVEN FURTHER REDUCTION!!

      How many times do you really want me to explain exactly the same thing to you?

      Comment


      • #23
        Originally posted by duby229 View Post
        IT'S AN EVEN FURTHER REDUCTION!!
        Yeah x86 ISA (not uop or uarch, but the ISA!!!) must be super RISC then considering some of its "CISC" instructions do several things you can do in other instructions, i.e. they're a "fusion" right?

        Let's look at the x86 leave instruction, that is for some reason considered CISC by many, maybe you should argue with them?

        I mean this instruction is literally a fusion of two instructions:
        Code:
        mov esp, ebp
        pop ebp
        Equivalent with that sequence. And pop can already be considered a fusion of two instructions:
        Code:
        mov ebp, [esp]
        lea esp, [esp+4]
        And since fusion = RISC that means x86 is more RISC than ARM for having such double fused instructions!!! Right?

        call is also a fused instruction, which for some reason RISC CPUs like ARM do not have and have to manually set up the stack frame with smaller instructions. I wonder why since fusion is definitely RISC!!!!!!!!!! ARM is FAKE!!!! x86 ISA TRUE RISC!!!

        Absolute clown.
        Last edited by Weasel; 08 August 2024, 10:19 AM.

        Comment


        • #24
          Originally posted by Weasel View Post
          Yeah x86 ISA (not uop or uarch, but the ISA!!!) must be super RISC then considering some of its "CISC" instructions do several things you can do in other instructions, i.e. they're a "fusion" right?

          Let's look at the x86 leave instruction, that is for some reason considered CISC by many, maybe you should argue with them?

          I mean this instruction is literally a fusion of two instructions:
          Code:
          mov esp, ebp
          pop ebp
          Equivalent with that sequence. And pop can already be considered a fusion of two instructions:
          Code:
          mov ebp, [esp]
          lea esp, [esp+4]
          And since fusion = RISC that means x86 is more RISC than ARM for having such double fused instructions!!! Right?

          call is also a fused instruction, which for some reason RISC CPUs like ARM do not have and have to manually set up the stack frame with smaller instructions. I wonder why since fusion is definitely RISC!!!!!!!!!! ARM is FAKE!!!! x86 ISA TRUE RISC!!!

          Absolute clown.
          I've already explained the difference between architecture and microarchitecture. You're the dumbass that can't understand the difference between instructions and micro-ops.

          EDIT: WHEN x86 was a true CISC microarchitecture like the 486, there was no such thing as micro-ops or a frontend. x86 could not be fully pipelined. WHEN it became a true RISC microarchitecture like the Pentium Pro, that's when it was fully pipelined and gained a frontend and a backend and translated instructions into micro-ops. And from there as fabrication nodes improved and transistor budgets got higher the backend micro-ops became more capable than the frontend instructions. And THAT is the reason for micro-op fusion!! It's a further reduction!!
          Last edited by duby229; 08 August 2024, 10:47 AM.

          Comment


          • #25
            Originally posted by duby229 View Post
            I've already explained the difference between architecture and microarchitecture. You're the dumbass that can't understand the difference between instructions and micro-ops.

            EDIT: WHEN x86 was a true CISC microarchitecture like the 486, there was no such thing as micro-ops or a frontend. x86 could not be fully pipelined. WHEN it became a true RISC microarchitecture like the Pentium Pro, that's when it was fully pipelined and gained a frontend and a backend and translated instructions into micro-ops. And from there as fabrication nodes improved and transistor budgets got higher the backend micro-ops became more capable than the frontend instructions. And THAT is the reason for micro-op fusion!! It's a further reduction!!
            Nobody gives a shit of what YOU claim, dumbass.

            Being pipelined has nothing to do with being RISC. YOU KEEP CLAIMING IT but that DOES NOT make it a fact, clown. Stop talking like it's fact and that we have to go from there. No, you haven't provided a shred of evidence that your bullshit claims are fact about it being RISC. Superscalar has nothing to do with RISC either.

            You have no fucking idea what you're talking about, you have no fucking idea of any definitions, you only make your shit claims as if they're fact and you think I'm supposed to accept them?

            You can keep repeating it like you said, it won't make it fact, just like claiming the Earth is flat won't make it fact no matter how many times you repeat it.

            Nobody cares about your opinions or made up definitions of RISC/CISC or whatever.

            Fusion is CISC as I proved above. Period. Either that, or the x86 ISA, not uarch, but ISA, is RISC. Pick your poison.
            Last edited by Weasel; 08 August 2024, 05:25 PM.

            Comment


            • #26
              Originally posted by Weasel View Post
              Nobody gives a shit of what YOU claim, dumbass.

              Being pipelined has nothing to do with being RISC. YOU KEEP CLAIMING IT but that DOES NOT make it a fact, clown. Stop talking like it's fact and that we have to go from there. No, you haven't provided a shred of evidence that your bullshit claims are fact about it being RISC. Superscalar has nothing to do with RISC either.

              You have no fucking idea what you're talking about, you have no fucking idea of any definitions, you only make your shit claims as if they're fact and you think I'm supposed to accept them?

              You can keep repeating it like you said, it won't make it fact, just like claiming the Earth is flat won't make it fact no matter how many times you repeat it.

              Nobody cares about your opinions or made up definitions of RISC/CISC or whatever.

              Fusion is CISC as I proved above. Period. Either that, or the x86 ISA, not uarch, but ISA, is RISC. Pick your poison.
              Dude, you're fucking stupid, moron.

              THEE defining feature of CISC microarchitectures is that their microcodes had interdependencies on each other and so all microcodes had to complete on the same clock cycles. While it is true that theoretically CISC architectures can be pipelined, in practice x86 never was because their microcode dependencies couldn't be fixed. The last x86 CISC microarchitecture was the 586 and it was NOT pipelined!! It did have additional transitions encoded on the main clock cycles edges so that more cycles could be completed within the main cycle, but this wasn't a true pipeline, it was a pseudo pipeline!!! X86 was not pipelined until it transitioned to a RISC microarchitecture!!!

              You are super fucking dumb and all because you WANT to be ignorant. Wtf?? Who the fuck desires to be supremely stupid!? Why do you choose ignorance?!
              Last edited by duby229; 09 August 2024, 09:05 AM.

              Comment


              • #27
                Originally posted by duby229 View Post
                THEE defining feature of CISC microarchitectures is that their microcodes had interdependencies on each other and so all microcodes had to complete on the same clock cycles.
                Prove it you delusional shithead. I'm fucking sick of your made-up bullshit. Especially the clock cycle part, where CISC is known to have wild varying clock cycle cost per different instructions (because it's CISC, makes sense, since each instruction can be wildly different/more complex than others).

                I don't give a fuck what you claim or what you THINK the definition is, which is clearly the complete opposite for any sensible human being with a bit of brain.

                Prove it with an authoritative link (not some random dumbass bitch on some random blog, which is same as you, a shitty opinion) or shut it.

                Comment


                • #28
                  CISC and RISC represent two fundamental approaches to processor design, each with its unique strengths and trade-offs. CISC focuses on complex instructions and flexible addressing, while RISC emphasizes simplicity and efficiency. Both architectures have evolved to address the needs of modern computing, with CISC processors incorporating RISC-like techniques and RISC designs pushing the boundaries of performance and power efficiency. mykohlscard

                  Comment

                  Working...
                  X