True CISC processors like a 486 had a frontend that is like a script interpreter and true RISC processors like a Pentium Pro had a frontend that is like a runtime compiler...
On the 486 there was a ROM that stored all the microcode Each microcode was essentially a tiny app for programming hardware registers. Each x86 instruction was essentially a script of microcodes that had to be capable of completing in 1 cycle. It didn't matter how long instructions were as long as they could complete in one cycle. It was 1 cycle because each instruction had nonlinear interdependencies between the microcode components and that made it impossible to pipeline the architecture.
On the Pentium Pro there was a decoder that translated the old instructions directly into micro-ops. Almost all of them could be translated into a direct 1 to 1 equivalent. The R in RISC means reduced, but reduced does not mean smaller or simpler. Reduced means that all the microcode that used to make up an instruction got compiled into a single self standing independent micro-op. And because of the nature of what micro-ops are they are much bigger than microcodes used to be. They do not have the interdependency problems that microcode had so the architecture could be pipelined, it could be out of order, it could be superscalar.
EDIT: This is why I keep stressing the fact that x86 instructions get decoded into direct 1 to 1 micro-ops... It's the ACTUAL definition of RISC..
EDIT: You can't call the frontend CISC and the backend RISC, that's not how it works. The frontend and the backend work together to make a complete architecture. The frontend decodes instructions into micro-ops and the backend executes them. The -entire- architecture is RISC.
On the 486 there was a ROM that stored all the microcode Each microcode was essentially a tiny app for programming hardware registers. Each x86 instruction was essentially a script of microcodes that had to be capable of completing in 1 cycle. It didn't matter how long instructions were as long as they could complete in one cycle. It was 1 cycle because each instruction had nonlinear interdependencies between the microcode components and that made it impossible to pipeline the architecture.
On the Pentium Pro there was a decoder that translated the old instructions directly into micro-ops. Almost all of them could be translated into a direct 1 to 1 equivalent. The R in RISC means reduced, but reduced does not mean smaller or simpler. Reduced means that all the microcode that used to make up an instruction got compiled into a single self standing independent micro-op. And because of the nature of what micro-ops are they are much bigger than microcodes used to be. They do not have the interdependency problems that microcode had so the architecture could be pipelined, it could be out of order, it could be superscalar.
EDIT: This is why I keep stressing the fact that x86 instructions get decoded into direct 1 to 1 micro-ops... It's the ACTUAL definition of RISC..
EDIT: You can't call the frontend CISC and the backend RISC, that's not how it works. The frontend and the backend work together to make a complete architecture. The frontend decodes instructions into micro-ops and the backend executes them. The -entire- architecture is RISC.
Comment