ARM Launches "Facts" Campaign Against RISC-V

[blargh4]

Google what? I got the Wikipedia page for ASIC and the first statement pretty much nullifies this. Maybe you're confusing them with FPGAs. By programmable, I mean the code (instructions) itself, not just tweak a few settings.

No they're not the same. Software tells the CPU what to do in the CPU's "language". The language is RISC or CISC. RISC means the language is simple with few words of equal length (clock latency, not encoding) that can be combined for something you want to do. CISC means the language is complex with a lot of words and some more specialized than others, and each word takes a different time to process (again, clock latency).

One such CISC word can mean an entire phrase, such as the inverse reciprocal square root approximation I was talking about.

The difference is that the CPU understands the language/words and has dedicated parts of its brain dealing with it (dedicated hardware for the instructions).

There's no law that a RISC-style ISA couldn't have an instruction/extension like inverse reciprocal square root, especially if it's a meaningful performance win and the uarch pipelines it relatively efficiently with other instructions in its hardware. CPU designers aren't drawing pedantic distinctions between RISC and CISC, you are.

If RISC is so fundamentally gimped on performance, can you please explain why Apple's arm64 JS engine running on my iPad Pro outperforms all JS engines running on the Skylake/Haswell laptops I use, and does so with only a heat spreader? Can you explain why during the 90s, high-end RISC processors typically outperformed x86/68k cores? Is it maybe, just maybe, possible that the microarchitecture/application-specific optimizations and extensions/implementation details are far more important aspects of high-performance CPUs than the base ISA?

[Tomin]

Something from early 1990s to better explain what RISC is: http://www.inf.fu-berlin.de/lehre/WS94/RA/RISC-9.html
To me it seems to boil down to fixed length instructions and load/store architecture (that's not exactly what that paper says though). Also, remember that language changes depending on how it is used. So while the first RISC might have had very simple instuctions, it really doesn't mean that a single instruction could not do more complex things.

[nanonyme]

Is the actual reference site the article's link pointed to now taken down? Looked pretty blank to me

[Michael]

Is the actual reference site the article's link pointed to now taken down? Looked pretty blank to me

Yes, Arm came under a great deal scrutiny and took down the site yesterday.

[xorbe]

I've worked on 2 arm chips, and that arch can DIAF. I don't understand why it's so popular. Other than I guess it's easier to make lower power than an x86 chip, but that's hardly a miracle.

[blargh4]

I've worked on 2 arm chips, and that arch can DIAF. I don't understand why it's so popular. Other than I guess it's easier to make lower power than an x86 chip, but that's hardly a miracle.

Companies license ARM IP because they offer many designs suitable for many applications, it's a big ecosystem with a long track record and many developers are familiar with it, and it has mature supporting infrastructure like OS support, compiler/debug/trace tools from multiple vendors, IP libraries, certifications, etc. A company designing silicon can just license a black-box ARM core and drop it into their product with relatively little effort/risk. Something like riscv isn't going to be competitive in those regards any time soon.

[coder]

But ASIC is not programmable,

This hasn't been true for decades.

[coder]

Your link says nothing about it by the way, other than Bitmain being a member (they could just use micro controllers in RISC V which don't matter).

Did you know Apple is a member of Khronos Group (who design Vulkan)? Proof that Apple uses Vulkan!!! Oh wait.

Those are not equivalent, because someone can belong to other SIGs in Khronos and have nothing to do with the Vulkan committee. On the other hand, your only interest in RISC-V membership is RISC-V.

A lot of bad points are not equivalent to a few good ones.

[coder]

Hmmm, I wonder what the likelier possibility is... that somehow a generation of CPU architecture researchers thought they could design a CPU with strong floating point performance by stringing together sequences of integer ops because hardware-acceleration is somehow anathema to the RISC idea, or that you're attacking a strawman?

I suspect you're onto something. I think our friend is more interested in winning arguments than the means by which this is achieved.

I've said it before: this whole debate is anachronistic and largely irrelevant. Many have pointed out that the line between CISC and RISC is blurring. Many of the benefits originally exclusive to RISC have been enjoyed by other ISAs, for a long time. As such, this abstract weighing of CISC vs. RISC philosophies should be confined to the dustbins of history.

Time will tell just how strong RISC-V's ISA really is. It's not like we're investors with $Billions at stake, so people should just relax and let it play out. And if RISC-V achieves a good amount of success, then perhaps the real game changer will be RISC-VI. RISC-V doesn't have to be be the best at everything to gain inroads and build momentum, and that's enough.

[oiaohm]

No they're not the same. Software tells the CPU what to do in the CPU's "language". The language is RISC or CISC. RISC means the language is simple with few words of equal length (clock latency, not encoding) that can be combined for something you want to do. CISC means the language is complex with a lot of words and some more specialized than others, and each word takes a different time to process (again, clock latency).

One such CISC word can mean an entire phrase, such as the inverse reciprocal square root approximation I was talking about.

Risc is not that straight forwards. Lot of historic RISC have each instruction of equal length and equal processing time. Please not I used the word most. Some did have longer clocks required for particular stores.

Risc-v is the fifth version of risc from Berkeley. https://en.wikipedia.org/wiki/DLX DLX is one of risc-v parents Sorry DLX chips did not have all the instructions taking the same amount of clock cycles. Like writing out to Ram could be slower.

RISC="Reduced instruction set computer" does not say that instructions have to be processed in the same amount of time. Yes its been normal for CISC to have instructions taking very different amounts of time. But it has not be strange for different RISC cpu to have this behaviour as well.

https://en.wikipedia.org/wiki/Reduced_instruction_set_computer

This is typical features of a risc. Please note there are many no typical risc processes out there.
Processor average throughput nears 1 instruction per cycle
1 instruction per cycle there are tones of risc cpu with out of order that do way more than 1 per cycle and there are examples like DLX that does at times less than 1.
In order risc-v depending on the cpu design might be doing 1 per cycle or mix of multi and singles per cycle.
Out of order risc-v still up in the air.
Uniform instruction format, using single word with the opcode in the same bit positions for simpler decoding
All variable encoded risc break this one.

https://en.wikipedia.org/wiki/Comparison_of_instruction_set_architectures

Yes there are quite a few variable risc instruction sets out there.
All general purpose registers can be used equally as source/destination in all instructions, simplifying compiler design (floating point registers are often kept separate)
I don't know of a risc where this is not true. There could be one out there.
Simple addressing modes with complex addressing performed by instruction sequences
Powerpc risc design breaks that one.

Few data types in hardware (no byte string or BCD, for example)
This is normally not broken in the instruction set in risc chips but you do see accelerators on risc chips doing this kind of stuff.

Risc-v is still a reduced instruction set. Most historic risc chips have had complex maths processors.

Weasel basically you have a lot of incorrect presumes about risc.

Lot of the compares between CISC and RISC has been Variable CISC vs Fixed RISC. Variable CISC vs Variable RISC is totally different problem. Risc-v instruction set is a Variable Risc. Risc out of order processor are all Variable processing time.

Risc-v is Variable Risc in encoding. Risc-v also Fixed and Variable processing time depending on what Risc-v cpu you have. Risc-v rocket and boom are not the first variable processing time RISC.

The vector system Risc-v has comes from cray systems for Risc cores. The vector in Risc-v is not CISC way of doing it. Vector Its programmable logic and risc based. Operations in Risc-v vector work out size of operation based on the register they are work on. Yes this is having the feature of risc of being able to use all registers in a area as source and destination vector adds extra wrinkle of those source and destinations being able to be different sizes without putting that in the instruction.

https://riscv.org/wp-content/uploads/2016/12/Wed0930-RISC-V-Vectors-Asanovic-UC-Berkeley-SiFive.pdf

Read down notice you are using normal risc-v add and sub and other operations on your vector allocated.

This is not like SSE, AVX, AVX-512 ... in lot of CISC designs where you added a new special processor you have now duplicated stacks of instructions. Rule of risc you don't without reason duplication instruction set function.

Vector is just a method to allow really effective in order massive Parnell or help in out of order allocation.

Risc-v is basically keep your instruction simple. Do complexity in out of order or careful in order instruction execution. It makes sense of a inorder cpu with instructions one after each other that don't conflict and will not need to be rolled back to be all executed in 1 cycle. One of the things risc-v rocket experiments are find in a lot of old risc designed did not look forwards down instructions enough. So were not executing as much as they could in 1 clock cycle.