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ARM Launches "Facts" Campaign Against RISC-V

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  • #91
    Originally posted by tjukken View Post
    Sigh. Just google it..
    Google what? I got the Wikipedia page for ASIC and the first statement pretty much nullifies this. Maybe you're confusing them with FPGAs. By programmable, I mean the code (instructions) itself, not just tweak a few settings.

    Originally posted by tjukken View Post
    Software tells the CPU what to do. RISC, CISC, it's all the same in that regard.
    No they're not the same. Software tells the CPU what to do in the CPU's "language". The language is RISC or CISC. RISC means the language is simple with few words of equal length (clock latency, not encoding) that can be combined for something you want to do. CISC means the language is complex with a lot of words and some more specialized than others, and each word takes a different time to process (again, clock latency).

    One such CISC word can mean an entire phrase, such as the inverse reciprocal square root approximation I was talking about.

    The difference is that the CPU understands the language/words and has dedicated parts of its brain dealing with it (dedicated hardware for the instructions).
    Last edited by Weasel; 07-11-2018, 03:06 PM.

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    • #92
      Originally posted by Weasel View Post
      Google what? I got the Wikipedia page for ASIC and the first statement pretty much nullifies this. Maybe you're confusing them with FPGAs. By programmable, I mean the code (instructions) itself, not just tweak a few settings.

      No they're not the same. Software tells the CPU what to do in the CPU's "language". The language is RISC or CISC. RISC means the language is simple with few words of equal length (clock latency, not encoding) that can be combined for something you want to do. CISC means the language is complex with a lot of words and some more specialized than others, and each word takes a different time to process (again, clock latency).

      One such CISC word can mean an entire phrase, such as the inverse reciprocal square root approximation I was talking about.

      The difference is that the CPU understands the language/words and has dedicated parts of its brain dealing with it (dedicated hardware for the instructions).
      There's no law that a RISC-style ISA couldn't have an instruction/extension like inverse reciprocal square root, especially if it's a meaningful performance win and the uarch pipelines it relatively efficiently with other instructions in its hardware. CPU designers aren't drawing pedantic distinctions between RISC and CISC, you are.

      If RISC is so fundamentally gimped on performance, can you please explain why Apple's arm64 JS engine running on my iPad Pro outperforms all JS engines running on the Skylake/Haswell laptops I use, and does so with only a heat spreader? Can you explain why during the 90s, high-end RISC processors typically outperformed x86/68k cores? Is it maybe, just maybe, possible that the microarchitecture/application-specific optimizations and extensions/implementation details are far more important aspects of high-performance CPUs than the base ISA?

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      • #93
        Something from early 1990s to better explain what RISC is: http://www.inf.fu-berlin.de/lehre/WS94/RA/RISC-9.html
        To me it seems to boil down to fixed length instructions and load/store architecture (that's not exactly what that paper says though). Also, remember that language changes depending on how it is used. So while the first RISC might have had very simple instuctions, it really doesn't mean that a single instruction could not do more complex things.

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        • #94
          Is the actual reference site the article's link pointed to now taken down? Looked pretty blank to me

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          • #95
            Originally posted by nanonyme View Post
            Is the actual reference site the article's link pointed to now taken down? Looked pretty blank to me
            Yes, Arm came under a great deal scrutiny and took down the site yesterday.
            Michael Larabel
            http://www.michaellarabel.com/

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            • #96
              I've worked on 2 arm chips, and that arch can DIAF. I don't understand why it's so popular. Other than I guess it's easier to make lower power than an x86 chip, but that's hardly a miracle.

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              • #97
                Originally posted by xorbe View Post
                I've worked on 2 arm chips, and that arch can DIAF. I don't understand why it's so popular. Other than I guess it's easier to make lower power than an x86 chip, but that's hardly a miracle.
                Companies license ARM IP because they offer many designs suitable for many applications, it's a big ecosystem with a long track record and many developers are familiar with it, and it has mature supporting infrastructure like OS support, compiler/debug/trace tools from multiple vendors, IP libraries, certifications, etc. A company designing silicon can just license a black-box ARM core and drop it into their product with relatively little effort/risk. Something like riscv isn't going to be competitive in those regards any time soon.
                Last edited by blargh4; 07-11-2018, 06:48 PM.

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                • #98
                  Originally posted by Weasel View Post
                  But ASIC is not programmable,
                  This hasn't been true for decades.

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                  • #99
                    Originally posted by Weasel View Post
                    Your link says nothing about it by the way, other than Bitmain being a member (they could just use micro controllers in RISC V which don't matter).

                    Did you know Apple is a member of Khronos Group (who design Vulkan)? Proof that Apple uses Vulkan!!! Oh wait.
                    Those are not equivalent, because someone can belong to other SIGs in Khronos and have nothing to do with the Vulkan committee. On the other hand, your only interest in RISC-V membership is RISC-V.

                    A lot of bad points are not equivalent to a few good ones.

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                    • Originally posted by blargh4 View Post
                      Hmmm, I wonder what the likelier possibility is... that somehow a generation of CPU architecture researchers thought they could design a CPU with strong floating point performance by stringing together sequences of integer ops because hardware-acceleration is somehow anathema to the RISC idea, or that you're attacking a strawman?
                      I suspect you're onto something. I think our friend is more interested in winning arguments than the means by which this is achieved.

                      I've said it before: this whole debate is anachronistic and largely irrelevant. Many have pointed out that the line between CISC and RISC is blurring. Many of the benefits originally exclusive to RISC have been enjoyed by other ISAs, for a long time. As such, this abstract weighing of CISC vs. RISC philosophies should be confined to the dustbins of history.

                      Time will tell just how strong RISC-V's ISA really is. It's not like we're investors with $Billions at stake, so people should just relax and let it play out. And if RISC-V achieves a good amount of success, then perhaps the real game changer will be RISC-VI. RISC-V doesn't have to be be the best at everything to gain inroads and build momentum, and that's enough.

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