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Bettering Radeon Gallium3D Performance With PCI-E 2.0

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  • #11
    Originally posted by Azpegath View Post
    Unless they start merging stuff from Catalyst to the FOSS drivers. I don't quite understand why they don't do that. I assume that the FOSS devs have access to the closed source code for Catalyst. I mean, what's the difference between merging actual Catalyst code and re-implementing it from open specifications? In the end, the functionality (and to some extent the code) should be the same.
    For one Catalyst is written in C++ and the kernel code and mesa are written in C
    Last edited by FireBurn; 20 January 2012, 08:21 AM. Reason: typo

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    • #12
      Originally posted by darkbasic View Post
      Just in time for PCI-E 3.0
      Didn't image such a big boost, at least in Windows the boost is very little with pci-e 2.0
      On Windows, the boost was very small with PCIe 2.0.
      Windows has PCIe 2.0 support from day 1. Back in those days, the cards available couldn't use the added bandwidth, but if you'd do the tests today, you'd definitely see bigger gains.

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      • #13
        Originally posted by darkbasic View Post
        Just in time for PCI-E 3.0
        Didn't image such a big boost, at least in Windows the boost is very little with pci-e 2.0
        This highlights a problem in mesa - mainly, it moves more data over the bus than the Windows drivers.

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        • #14
          Originally posted by Azpegath View Post
          Unless they start merging stuff from Catalyst to the FOSS drivers. I don't quite understand why they don't do that. I assume that the FOSS devs have access to the closed source code for Catalyst. I mean, what's the difference between merging actual Catalyst code and re-implementing it from open specifications? In the end, the functionality (and to some extent the code) should be the same.
          We do not have access to the catalyst source code due to the fact that it contains 3rd party code that's not ours to release. Additionally, the actual software stacks are very different and largely incompatible.

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          • #15
            But I imagine looking at e.g. the power saving code could still tell a very good programmer why radeon on the "low" profile still uses more power than fglrx.

            I mean, why doesn't AMD simply have somebody going over the code of catalyst, deleting everything patented or "secret" and release the nonfunctional rest? Could still be helpful for low level stuff like power saving and communicating properly with the hardware...

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            • #16
              Originally posted by ChrisXY View Post
              But I imagine looking at e.g. the power saving code could still tell a very good programmer why radeon on the "low" profile still uses more power than fglrx.

              I mean, why doesn't AMD simply have somebody going over the code of catalyst, deleting everything patented or "secret" and release the nonfunctional rest? Could still be helpful for low level stuff like power saving and communicating properly with the hardware...
              That's legal territory. Do not attempt to apply logic.

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              • #17
                Originally posted by ChrisXY View Post
                But I imagine looking at e.g. the power saving code could still tell a very good programmer why radeon on the "low" profile still uses more power than fglrx.

                I mean, why doesn't AMD simply have somebody going over the code of catalyst, deleting everything patented or "secret" and release the nonfunctional rest? Could still be helpful for low level stuff like power saving and communicating properly with the hardware...
                by the time thats get done mesa 12.1 would be the distro standard version, beside that code is useless for mesa is like asking microsoft to release their kernel code to improve linux powermanagement in laptops.

                mesa ppl already knows very clearly (prolly) what all the missing bits are and globally whats needed to face catalyst very close, what ppl seems to don't understand no matter how many times is explained is that mesa have like 5 DEVELOPERS and the code to handle GPU is EXTREMELY COMPLEX so is not like you can't magically shave out of your ass a couple of houndred thousand of lines code to magically make all work

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                • #18
                  I just have the bad feeling that AMD will lose against intel in the GPU side too, on Linux.
                  I wished they could focus on one thing but make it right.
                  Missing features from r600g are 2D Tiling,HiZ, apparently PCI-E2, power saving. Why it is a problem for AMD employee to look at the catalyst, and see how these features are implemented(registers involved, state transitions, specific chips code-paths, etc), and re implement them on r600g? I am not talking here about *super secret* shader compiler(which nvidia may steal, and somehow adapt to their totally different architecture), but just enablement code.

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                  • #19
                    Originally posted by bug77 View Post
                    That's legal territory. Do not attempt to apply logic.
                    I don't mean copy-paste. I mean actual rewrite, but the code was already R&D.
                    Apparently Intel are not afraid from legal issues.

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                    • #20
                      Originally posted by ChrisXY View Post
                      But I imagine looking at e.g. the power saving code could still tell a very good programmer why radeon on the "low" profile still uses more power than fglrx.

                      I mean, why doesn't AMD simply have somebody going over the code of catalyst, deleting everything patented or "secret" and release the nonfunctional rest? Could still be helpful for low level stuff like power saving and communicating properly with the hardware...
                      The main problem is the sheer size of the Catalyst code relative to the size of the open source dev team. We tried sanitizing a much smaller code base (the "tcore" diagnostic platform) to kickstart r6xx support... spent ~9 months of part-time work on it and eventually gave up. The Catalyst power management code alone is bigger than the entire open driver stack.

                      The challenge enabling things like tiling isn't "not knowing how to enable", it's that enabling tiling requires changes in a lot of different places and since the driver architectures are different you can't just look at the proprietary driver and find the corresponding areas in the open driver.
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