Open ATI R600/700 Driver Gains Tiling Support

[Perry3D]

Are there new patches that apply to the DDX master branch?

patching file src/r6xx_accel.c
Hunk #2 FAILED at 910.
Hunk #3 FAILED at 926.
2 out of 3 hunks FAILED -- saving rejects to file src/r6xx_accel.c.rej

patching file src/radeon_dri2.c
Hunk #1 FAILED at 102.
Hunk #2 succeeded at 107 (offset -3 lines).
Hunk #3 FAILED at 192.
2 out of 3 hunks FAILED -- saving rejects to file src/radeon_dri2.c.rej

Or did i miss something?

[jrch2k8]

They'll be in 2.6.36.

that make me sad on my pants

but i know will worth it so that make me happy on my pants

funnier expression i've seen in a movie

[pingufunkybeat]

Thanks.

I think I'll wait for them to hit git and then test it with the radeon-testing kernel. But I'm quite excited about this + power management stuff.

[agd5f]

Yet to be determined. There are still some corner cases that need to be fixed up.

[pingufunkybeat]

Any plans for when the Mesa and DDX patches will hit git?

[agd5f]

They'll be in 2.6.36.

[bridgman]

I don't think so. They're in drm-radeon-testing but not in 2.6.35.

[jrch2k8]

this patches made it to kernel 2.6.35 -rcX?

im trying to test the latest 2.6.35-rc2 kernel and xorg still informs color tiling is not available for r600/700 chips, in that case someone knows if xorg edgers included the color tiling patches?

im kinda busy to patch all myself these days

in case all the previous are yes, then my 4850x2 isn't recognzed yet

otherwise i'll test it later

[bridgman]

I did a quick search and didn't find any useful articles, so here's a quick summary :

Tiling refers to the way that X/Y addresses in the GPU are mapped onto chip addresses in the video memory. It makes a big difference because video memory chips are normally organized into rows, where access to a series of locations within a row is *much* faster than access to a series of locations in different rows. GPU cache lines tend to be organized the same way, since GPUs use burst transfers to move part of a memory row between video memory and on-chip cache lines.

By default the video memory attached to a GPU is organized so that increasing memory addresses correspond to points starting in the top left corner of a surface (a surface could hold image data, depth info or texture), increasing as you move to the right across the surface, then resuming at the left edge of the next row down. That default mapping is often called "linear", because a row of memory corresponds to a series of horizontal lines running the full width of the screen.

With me so far ?

OK, now let's look at drawing a typical set of triangles. Drawing tends to happen in an area that is closer to square than to a horizontal line, ie you're likely to see a series of triangles drawn in the same 200x200 pixel area, not scattered evenly across the width of the surface. What that means is the drawing operation touches on a lot of memory rows (since memory rows are the full width of the surface), which means a lot of memory accesses are required.

What would be great would be if memory rows could correspond to square or rectangular areas rather than horizontal lines. Tiling is basically some shuffling of address lines between GPU and memory controller so that a row of memory corresponds to a series of "tiles" which increases the chance that a series of drawing operations will hit in the same memory row or cache line. Put differently, it decreases the number of memory rows / cache lines required to cover a typical cluster of drawing operations.

The final stage of image drawing on a 6xx or higher GPU is done by a block called the Color Buffer (CB), so color tiling refers to tiled image surfaces. Z-buffer operations are handled by a block called the Depth Buffer (DB), so Z tiling is also referred to as depth tiling. The other candidate for tiling is textures. In each case the blocks include one or more registers indicating what kind of tiling should be used when accessing video memory through that block.

The challenge with tiling is that occasionally software rendering is required. Since the address lines have been swizzled between GPU and memory controller, reading the memory directly with CPU will result in a scrambled image. The driver changes to support tiling include routines to convert to/from tiled areas.

[Drago]

Can I read somewhere, what actually is Color Tiling, and what it is good for?