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AMD Lands A Number Of RadeonSI RDNA NGG Fixes Ahead Of RDNA3 Enabling

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  • #11
    Originally posted by brucethemoose View Post
    Another thing I want to ask the AMD driver people: are there any changes specifically for the upcoming multi-chip GPUs?
    if you see the first multi chip cpus like threadripper 1950X it can emulate a cpu without chiplet design and it can run in numa node mode.
    the 1950X threadripper has 2 ram channel per chiplet and cross links between the chiplet
    the 2990WX and 2970WX can only run in numa node mode because 2 chiplets have 2 64bit ram channel and 2 only sit on the cross links without having any ram at all for their own need.

    for RDNA3 in the past i thought they make a big IO cross bar chiplet and 2 gpu chips sharing the vram on the IO cross bar... but this will not be the case because the overhead of sync the complete data between these 2 gpu cores will be to much overhead in the IO crossbar.

    no the RDNA3 design willl be more like the threadripper 1950X design but instead of only cross talking lines between 2 gpu dies they will have a IO crossbar in the middle with infinity cache and every gpu will have their own GDDR6 ram channel controller. by this every gpu only need to sync some and not all data over the IO crossbar. and some data can still be shared over all ram channels to use the full vram of all chiplets.

    in the past if you had dualgpu and 16gb vram you could only use 8gb vram with that design if you have 16gb vram you can use full 16gb for stuff you dont need "sync" and 8gb+ for stuff you need to sync.

    also remember this: the first RDNA3 card will not have 2gpu chiplets + IO die but instead the radeon7700XT will only have 1 GPU chiplet and the IO die.

    they realase this 7700 first because they need 6month or more to implement the driver to utilize the full 2 cpu chiplet plus IO die what will not be trivial...

    but who cares the 7700 will have 6950XT level performance with only 12gb vram the full 7900XT will have 24gb vram.

    Phantom circuit Sequence Reducer Dyslexia

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    • #12
      Michael , unfortunately, WCCFTech is now publishing some articles copied from Phoronix without giving the proper source link, as well as NOT setting the canonical url on the source code to point to your original article.

      Look at the following article:
      https://wccftech.com/amd-receives-se...u-architecture

      They need to be notified. They are wrong.
      Last edited by paulocoghi; 13 June 2022, 06:46 PM.

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