Originally posted by coder
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Originally posted by coder
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Originally posted by coder
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Originally posted by coder
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Originally posted by coder
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You have been stupid tunnel visioned here. L1, L2 and L3 cache in the GPU die is not all vmem there are missing features when you get to virtualisation. Yes consumer cards are sold with out MxGPU and Vgpu because 1 market segmentation 2 the security on the vmem has a performance cost. So if you are sharing a GPU between multi virtual machines do you really want to be processing security every time you transfer into L3 to L2 or would not not want to do this between L4 and L3. Remember early PC only had a L1 and 12 at best when we added to PC cpus L3 we did not go and rename mmu/main memory right.
Vmem is your GPU form of main memory and is meant to be the full feature memory.
LX number is the level of cache. Vmem location makes it a particular level of cache. But Vmem does not just do cache.
The reality is a in die L3 in the modern AMD GPU is not a vmem it does not have the security features. Yes those security features include what memory is accessible by DMA over PCIe.
CXL has the security implemented in CXL protocol.
Yes you vramless gpus will look a lot like your current desktop GPUs just with everything in the die but these are not the ones you use in virtual machine setups as they are missing MxGPU and Vgpu in most cases.
There is one big difference between a AMD L3 in die cache and the old Vram being used as cache/l3. Vram has a MMU the L3 in die does not have a MMU.
vramless gpus could coming could also be-called mmuless GPUs.
Another thing to remember a GPU memory size on the specification sheet states the vram size not the on die cache memory size as well. So a GPU with a L3 of 4G on die but as a vramless on specification sheet would have a GPU memory size of 0. So yes people who see a specification sheet of a vramless gpu prototype think that there has to be a error because a GPU cannot work with zero memory right.
Reality vram and in die cache are written independently on the specification sheets as well.
Originally posted by coder
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