Hashcat 6.2.3 Introduces AMD HIP Backend

[phoronix]

Phoronix: Hashcat 6.2.3 Introduces AMD HIP Backend

Released on Friday was a new version of the Hashcat open-source password recovery tool that now adds an AMD HIP back-end...

https://www.phoronix.com/scan.php?page=news_item&px=Hashcat-6.2.3-HIP

[ms178]

Even though it would be just a single data point, it would be interesting to see if the performance of the HIP backend is on par with the ROCm backend.

[hoohoo]

I hope the git branch for this was named "Hipcat"!

[Mathias]

Even though it would be just a single data point, it would be interesting to see if the performance of the HIP backend is on par with the ROCm backend.

And CUDA on the other side - actually CUDA is even more important. If CUDA doesn't take a hit, one can better argue to switch from CUDA to HIP. A 30% slower HIP on AMD is better then a 100% slower nothing on AMD.

[seesturm]

Even though it would be just a single data point, it would be interesting to see if the performance of the HIP backend is on par with the ROCm backend.

ROCm is an architecture without concrete interface. For using ROCm a supported interface has to be chosen. ROCm supports interfaces like HIP and OpenCL.

So it does not really make sense to ask how ROCm performance compares with HIP preformance.

[Paradigm Shifter]

I hope the git branch for this was named "Hipcat"!

Beat me to it!

...now I want to watch that Tom and Jerry episode "The Zoot Cat".

[bridgman]

ROCm is an architecture without concrete interface. For using ROCm a supported interface has to be chosen. ROCm supports interfaces like HIP and OpenCL.

So it does not really make sense to ask how ROCm performance compares with HIP preformance.

I haven't had a chance to confirm this, but I expect the earlier "ROCm" implementation is really an "HCC" implementation. The HCC compiler had a couple of different operating modes, IIRC one was more like C++ AMP and the other was HIP.