Originally posted by Ranguvar
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Whether a CPU core has in-order or out-of-order execution is completely independent on whether it has speculative execution.
Those CPU cores quoted by you have speculative execution, despite having in-order execution.
The difference between a CPU core with in-order execution and a CPU core with out-of-order execution is that when they encounter in the instruction stream an instruction with unsatisfied data dependencies (a.k.a. functional dependencies), the former stalls execution until the dependencies become satisfied, while the latter does not execute that instruction, but it continues to execute the instructions following it.
The difference between a CPU core without speculative execution and a CPU core with speculative execution is that when they encounter in the instruction stream an instruction with unresolved flow of control dependencies (i.e. an instruction that is a conditional branch or which follows one or more conditional branches with unresolved conditions), the former stalls execution until the dependencies are resolved, while the latter executes that instruction, by guessing the values of the conditions of which it depends.
Not only the out-of-order superscalar CPU cores need speculative execution, but even an in-order CPU that executes only one instruction per clock cycle requires speculative execution, if it is designed for a high clock frequency, so that it has a long execution pipeline.
Typically being in-order is associated with much more reduced capabilities of speculative execution, because increasing them would be pointless. If the CPU is in-order, the first instruction among the speculated instructions that has unsatisfied data dependencies will stall the execution anyway.
Nevertheless, even very feeble capabilities of speculative execution can make a CPU insecure, when the speculative execution is implemented wrongly, i.e. where if the instructions executed speculatively are canceled,, some effects of their execution still remain, e.g. in the state of the CPU cache memories.
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