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Intel Architecture Day 2021 & The Linux State

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  • #11
    Upon launch of Arc and specifically Xe HPG we're looking for about a 7 on the laugh scale, down from 9.5 last year.

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    • #12
      Hmm, as always Windows has better suport for desktop:

      "On the question of Linux, Intel only went as far to say that Windows 11 was the priority, and they’re working upstreaming a variety of features in the Linux kernel but it will take time. An Intel spokesperson said more details closer to product launch, however these things will take a while, perhaps months and years, to get to a state that could be feature-parity equivalent with Windows 11."

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      • #13
        Originally posted by HEL88 View Post
        Hmm, as always Windows has better suport for desktop:

        "On the question of Linux, Intel only went as far to say that Windows 11 was the priority, and they’re working upstreaming a variety of features in the Linux kernel but it will take time. An Intel spokesperson said more details closer to product launch, however these things will take a while, perhaps months and years, to get to a state that could be feature-parity equivalent with Windows 11."
        Naturally, there's tons of money and resources being poured into it.

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        • #14
          Originally posted by avem View Post
          The most important announcement is probably XeSS : vendor-neutral AI upscaler using motion vectors which promises to rival DLSS 2.0.


          Too bad Michael hasn't paid attention to it.

          FSR can be safely buried.
          The video was taken down! Did it go under embargo? o-o

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          • #15
            Originally posted by spykes View Post
            I think AVX-512 is a waste of silicon space on desktop CPUs, AVX2 covers all major use cases on a desktop and I would prefer to have more CPU cores than having AVX-512.

            I do not agree that AVX-512 is useless on desktop, because what is important in AVX-512 is not the greater width but the much more convenient instructions, which simplify programming. That is even more important on desktop than on servers, as on desktop a developer might frequently write programs that are intended to be used just a few times, so it is important to be able to write them quickly and not waste too much time with optimizing them.

            AVX is a crippled instruction set that should never have existed. Intel should have introduced in Sandy Bridge not AVX but a 256-bit version of the Larrabee New Instructions, which are called now AVX-512.

            However, in order to maximize profit, Intel has always added as few improvements as will still be accepted by customers, because making a better CPU raises the production cost, while the selling price remains the same.


            Nevertheless, even if you were right, the AVX-512 hardware still exists in Alder Lake, because the same Golden Cove cores are also used in Sapphire Rapids.

            So disabling AVX-512 does not give the owner any advantage, it just simplified the task of Microsoft, who did not have to find a solution to how to schedule threads that might have different requirements for the CPU features. Disabling AVX-512 has also raised Intel's yields, because otherwise defective chips where the defects happened to be in the AVX-512 registers or ALUs are now good chips that can be sold.















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            • #16
              Originally posted by atomsymbol

              I would prefer Intel to release two versions of desktop CPUs: with and without AVX-512.

              I am unable to find information about whether desktop P-cores (AVX-256) have the same instruction set as E-cores. Server E-cores seem not to support AVX-512, so x86 heterogeneity might start in server space.

              Anandtech says "Intel also stated that both the P-core and E-core will be at ‘Haswell-level’ AVX2 support."

              Much more precise information exists in the patch to the LLVM target description for Alder Lake.

              According to the LLVM patch, Gracemont and the Golden Cove core as configured for Alder Lake support the Broadwell instruction set, i.e. inclusive BMI1, BMI2 and ADX.

              Besides the Broadwell ISA, Alde Lake supports SHA from Goldmont, MOVDIRx & CLDEMOTE from Tremont, VNNI from Cascade Lake and some, but not all, of the non-AVX-512 instructions introduced by Ice Lake.

              So it looks that compared with Rocket Lake Alder Lake will miss both the AVX-512 instructions and a few other of the ISA extensions supported by Ice Lake and Rocket Lake.













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              • #17
                Originally posted by jaxa View Post
                The Gracemont cores reaching +40% performance over Skylake at the same power usage is a big highlight. It helps explain how a Core i9-12900K could outperform a Ryzen 9 5950X, while using a lot of energy. Those results probably use DDR5 while Skylake is stuck with DDR4.

                Edit: They are comparing 1C1T for both while the same Skylake core is capable of 1C2T, for another 30% or so multi-threaded performance. Still a good result.
                Note "at ISO power", which basically means at a certain power level. All this is saying is that Gracemont is 40% more energy efficient. That's also comparing across manufacturing nodes.
                So the result isn't normalised to same process. So the gains are a lot smaller than I think actually needed.

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                • #18
                  Originally posted by tildearrow View Post

                  The video was taken down! Did it go under embargo? o-o
                  No idea, that's really weird.

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                  • #19
                    on Anandtech.com they talked about the "Intel Thread Director" and not fully implemented

                    On the question of Linux, Intel only went as far to say that Windows 11 was the priority, and they’re working upstreaming a variety of features in the Linux kernel but it will take time. An Intel spokesperson said more details closer to product launch, however these things will take a while, perhaps months and years, to get to a state that could be feature-parity equivalent with Windows 11.
                    I guess this will have impact during the initial release, if the heavy processes are running on the e-cores and not being moved to to the p-cores, or delayed.

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                    • #20
                      The "Thread Director" is probably the marketing name for the hardware feedback interface (Chapter 13 in the document at [1]):
                      Basically the CPU constantly tells the OS at runtime how fast or energy efficient a core can go, and it's then up to the OS scheduler
                      to find the right task for each perf/efficiency level of a core. I'm sure it's not that easy figuring out what perf/efficiency class to assign to
                      any random executable.

                      [1] https://software.intel.com/content/d...-reference.pdf
                      Last edited by mlau; 20 August 2021, 07:05 AM. Reason: Link added

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