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Linux Kernel Prepares For Intel Xeon CPUs With On-Package HBM Memory

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  • #21
    Originally posted by ms178 View Post
    Guest That might be a factor, but when Intel brings PCIe 5 to market this year for a mainstream platform,
    Something doesn't smell right about that claim. Intel failed their initial PCIe 4.0 rollout, with Comet Lake, and we're expected to believe they're going to be first to market with PCIe 5.0 support and literally no devices or use cases? I don't. I think it'll only be used for some corner case, like the chipset link.

    Originally posted by ms178 View Post
    it wouldn't look good PR-wise to lack behind here by a significant amount of time.
    PR isn't the only thing that matters.

    Originally posted by ms178 View Post
    CXL is also a big technical advantage in terms of CPU+GPU+memory interaction
    When PCIe 4.0 offers only a marginal benefit over PCIe 3.0, I don't see the value of a consumer board with PCIe 5.0 or CXL.

    Originally posted by ms178 View Post
    We will see if VCache can make up for that deficit,
    VCache is completely different, and will be launching on AM4 chips this year. It only affects CPU performance (and does so by transparently expanding L3 cache), whereas CXL and PCIe 5.0 are I/O technologies.

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    • #22
      Originally posted by jayN View Post
      However, if CXL moves on-chip the bus widths can be large.
      First, why would a CPU use CXL to access in-package memory? That's unnecessary and would just add latency and probably burn more power.

      Second, even if it does, that's an internal detail. The point of CXL memory modules is that it gives you a cache-coherent means of scaling memory for an entire multi-device system. Therefore, CXL only becomes meaningful in a system context. And a CPU doesn't need to use CXL to interface with its in-package memory for that memory to be CXL-accessible to other nodes in the system -- the CPU just needs to support CXL, itslef.

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      • #23
        Originally posted by coder View Post

        When PCIe 4.0 offers only a marginal benefit over PCIe 3.0, I don't see the value of a consumer board with PCIe 5.0 or CXL.


        VCache is completely different, and will be launching on AM4 chips this year. It only affects CPU performance (and does so by transparently expanding L3 cache), whereas CXL and PCIe 5.0 are I/O technologies.
        You make it sound as it only effects sequential reads/writes on a M2-NVMe device but as CXL fundamentally changes how CPU+GPU+memory interacts together (more efficiently) I see a use case for this technology in every PC segment, not just servers and therefore a much larger impact on the industry as you make it sound. I don't like higher motherboard prices due to lazy engineering/reluctance to move to a new connector (SFF-TA-1002) either, but at least PCIe 4.0 was supposed to be the bigger step here with PCIe 5.0 refining over that work, hence the faster pace between the 4.0 and 5.0 specs. We will see if these claims will hold true in practice soon as the implementation might have been harder than anticipated. I also would like to remind the whole industry to get the costs in check, this would mean more clever engineering to cut costs (SFF-TA-1002 is cheaper to implement and more flexible, the spec is here already for several years - backwards compatibility concerns could be adressed as motherboards offer the space for legacy connectors). We used to see such hard cuts more often in the 90s and 00s (ISA -> PCI -> AGP -> PCIe).

        Losing the technological lead is "not only PR", this is huge in terms of mindshare for a platform. It is not just a number on a box but influences buying decisions, especially if your competitior could present a use case for gamers which would enhance the gaming experience with their CPU+GPUs or adds functionality in a big way (e.g. memory pools; if we see some of these added features in the consumer space remains to be seen).

        By the way, I am well aware that CXL and VCache are different technologies, my point was about the psychological impact on the market really. AMD wants to show off clever engineering of their own which could help them to keep the gaming crown from Alder Lake. After all people make their buying decisions on whose chip is on the top of the charts and price/performance; VCache could be a means for them to stay on top of these charts. If Intel came up with the more advanced platform which offers real benefits to gamers when used together with their upcoming Xe HPG lineup, that could swing the mindshare of people back into their camp and would make AM5 look very dated when it arrives in late 2022. All Intel needed to do is a demo of these benefits (thanks to CXL) before or at launch.
        Last edited by ms178; 13 June 2021, 04:24 AM.

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        • #24
          Originally posted by coder View Post
          The point of CXL memory modules is that it gives you a cache-coherent means of scaling memory for an entire multi-device system.
          The point is the asymmetric cache coherency.

          Intel is adding PCIE5 to Alder Lake.

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          • #25
            Originally posted by coder View Post
            First, why would a CPU use CXL to access in-package memory? That's unnecessary and would just add latency and probably burn more power.

            Second, even if it does, that's an internal detail. The point of CXL memory modules is that it gives you a cache-coherent means of scaling memory for an entire multi-device system. Therefore, CXL only becomes meaningful in a system context. And a CPU doesn't need to use CXL to interface with its in-package memory for that memory to be CXL-accessible to other nodes in the system -- the CPU just needs to support CXL, itslef.
            Right... the value of CXL is as a vendor-neutral interconnect - we have been shipping HBM-speed coherent on-die interconnect along with inter-die (GMI) and inter-package (XGMI) coherent links since 2017. Vega10 was the first GPU with on-die coherent fabric, while EPYC used GMI and XGMI in addition to the on-die fabric.

            CXL has the potential to be a cross-vendor alternative to XGMI for some applications, which makes it interesting. I thought the wccftech article was a bit misleading though, since it mixed the author's views with Intel's statements, and most of the comments about seamless multi-GPU operation seemed to be the author's opinion only.
            Last edited by bridgman; 13 June 2021, 06:06 PM.
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            • #26
              Originally posted by bridgman View Post

              Right... the value of CXL is as a vendor-neutral interconnect -
              Yes, it is true that the cache coherency is vendor-neutral, in that it doesn't force XPUs to implement someone's proprietary symmetric coherency.

              It also means you get the lowest latency accesses by an XPU to its attached memory while the xpu has the bias.

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              • #27
                Originally posted by coder View Post
                [Xeon Phi] You could drop it in the same socket as Skylake SP Xeons[...]
                No. Same number of pins, different socket.

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                • #28
                  Originally posted by ms178 View Post
                  as CXL fundamentally changes how CPU+GPU+memory interacts together (more efficiently) I see a use case for this technology in every PC segment,
                  I won't rule out the possibility, but that's not its primary purpose or its initial market.

                  Originally posted by ms178 View Post
                  I also would like to remind the whole industry to get the costs in check, this would mean more clever engineering to cut costs
                  Ah, you want to go back to cables? That'll cut PCIe 5.0 implementation costs, at the expense of regressing back to the "rats nest" era of PCs innards.

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                  • #29
                    Originally posted by jayN View Post
                    Intel is adding PCIE5 to Alder Lake.
                    It remains to be seen at what scale, though. Could be just for the DMI link. That would be a cheap and easy way for them to tick the PCIe 5.0 checkbox.

                    Then again, you seem pretty familiar with Intel's products and docs. If you can show me something with the new CPU socket spec that shows how many pins are carrying PCIe 5.0, please do.
                    Last edited by coder; 15 June 2021, 09:13 PM.

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                    • #30
                      Originally posted by coder View Post
                      I won't rule out the possibility, but that's not its primary purpose or its initial market.


                      Ah, you want to go back to cables? That'll cut PCIe 5.0 implementation costs, at the expense of regressing back to the "rats nest" era of PCs innards.
                      We might have different opinions and use cases in mind here, but please take a look at the TA-1002 connector and PECFF white paper, you can read about them at the GenZ-Consortium site. That is by far a more flexible and cost-effective solution [1]. Nvidia and Intel are already on board regards TA-1002, AMD is also involved via the GenZ-Consortium - it is just a matter of time until TA-1002 arrives at the market. The spec is out in the wild already for two years, so I am getting impatiant for a market release but instead these companies opted for letting us consumers pay the higher implementation costs of PCIE instead in the meantime.

                      [1] quotes from the PECFF white paper:
                      • PECFF supports the high-volume, fully-interoperable SFF-TA1002/Gen-Z Scalable Connectors. These connectors support up to 112 GT/s signaling, which will provide many years of use across multiple market segments without requiring redesign.
                      • PECFF has a low barrier for adoption as PECFF does not require new mechanical enclosures and is similarly sized to PCIe CEM AICs to take advantage of existing manufacturing infrastructure.
                      • PECFF eliminates the need for separate high-power cables and associated connectors. This reduces cost, manufacturing complexity, and improves serviceability. • When combined with the Gen-Z protocol, PECFF can support any component or media type.
                      • PECFF simplifies platform design and manufacturing
                      • Can eliminate the need for high-cost, low-loss board materials and retimers by reducing trace lengths
                      • Can use Gen-Z Scalable Connector internal cables to repurpose slots or to provide additional bandwidth/connectivity using topedge connectivity without requiring custom motherboards.
                      • Can support multiple links and multiple connectors to eliminate single points of failure and stranded resources, reducing the amount of replicated hardware and enable optimal resource use and provisioning.
                      • PECFF supports 48V, which provides greater power efficiency.
                      • PECFF allows for both active and passive air and liquid-based cooling.

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