Linux Kernel Prepares For Intel Xeon CPUs With On-Package HBM Memory

[phoronix]

Phoronix: Linux Kernel Prepares For Intel Xeon CPUs With On-Package HBM Memory

Last year Intel's updated ISA extensions reference guide was updated with references to Xeon "Sapphire Rapids" having High Bandwidth Memory (HBM) given new HBM-related error codes. Now it's even more clear there are Xeon CPUs coming to market with onboard HBM memory as Intel has begun submitting Linux kernel driver changes...

https://www.phoronix.com/scan.php?page=news_item&px=Linux-Prepares-Xeon-HBM

[Snaipersky]

I wonder who will make an iGPU-equipped CPU with HBM first... The colossal bandwidth afforded should mean that every thread in an 8c16t could receive 64GB/s and still have 1TB/s available to a GPU (assuming 4x2048bit@2GHz).
stick the whole package on a motherboard, and you could have a full workstation in less space than a 6-pack.

[kylew77]

Seems in line with what I read on this site: https://www.servethehome.com/server-...b-onboard-era/ The era of GBs of cache is coming supposedly.

[jayN]

I wonder who will make an iGPU-equipped CPU with HBM first...

Intel's Kaby Lake-G had their cpu, AMD's GPU and some HBM in one package.

[skeevy420]

I've always wished AMD would do that with their APUs. I could justify another $100+ for what I paid for my setup if it came with 4GB HBM instead of piggybacking the system memory.

[Snaipersky]

Intel's Kaby Lake-G had their cpu, AMD's GPU and some HBM in one package.

That They did, and to this day they've never made anything as good. Though, I was thinking shared memory for flexibility for compiles, renders, etc. If you can fit 2TB/s in one box, having that capacity available to both parts would seem most beneficial. 8c/16t and dg2sku1/3070ti/rx6800xt in 300-350W and 2L just sounds perfect. Throw in a dual port x550, TB4, and 2 gen4x4 m.2 slots, ho boy.

[jayN]

Though, I was thinking shared memory for flexibility for compiles, renders, etc.

CXL will enable mapping of GPU's HBM into CPU memory space. CPU would access it through L3 cache. We'll probably get some explanation of this at the Hotchips Sapphire Rapids and Ponte Vecchio presentations in August.

[ms178]

CXL is a huge enabling technology, that makes me wonder why AMD won't bring it to AM5 at launch with PCIe 5 as they will stay at PCIe 4.

[Guest]

CXL is a huge enabling technology, that makes me wonder why AMD won't bring it to AM5 at launch with PCIe 5 as they will stay at PCIe 4.

Maybe cost? Might be too costly for the normal consumer market.

[ms178]

Guest That might be a factor, but when Intel brings PCIe 5 to market this year for a mainstream platform, I would have expected AMD to come up with their own implementation a year later and to be mature enough for the mobo makers to implement it by then. Considering that AMD were first last generation, it wouldn't look good PR-wise to lack behind here by a significant amount of time. CXL is also a big technical advantage in terms of CPU+GPU+memory interaction so giving Intel an edge here to offer something better system-wise with Xe HPG would mean to lose the technical lead and mindshare to them again. We will see if VCache can make up for that deficit, but I had hoped to see them being more advanced with a new platform.