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Intel Continues Bringing Up DMA-BUF Support For RDMA

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  • Intel Continues Bringing Up DMA-BUF Support For RDMA

    Phoronix: Intel Continues Bringing Up DMA-BUF Support For RDMA

    Presumably with Xe-HP in mind, Intel engineers continue working on adding DMA-BUF support to the Linux kernel's RDMA code...

    http://www.phoronix.com/scan.php?pag...MA-BUF-RDMA-v3

  • #2
    I see that DMA-BUF driver mods associated with Infiniband. Are the similarities between Infiniband and RoCE, used by Intel's Habana NNPs, enough to expect the Habana NNP drivers to use DMA-BUF?

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    • #3
      Any info available that says Xe-HP is supposed to also support CXL? I see notebookcheck leaks this weekend that Alder Lake-S will include PCIE5 io, and am wondering if the PCIE5 presence hints that Xe GPUs other than Ponte Vecchio might support CXL.

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      • #4
        Originally posted by jayN View Post
        Any info available that says Xe-HP is supposed to also support CXL? I see notebookcheck leaks this weekend that Alder Lake-S will include PCIE5 io, and am wondering if the PCIE5 presence hints that Xe GPUs other than Ponte Vecchio might support CXL.
        I was under the impression CXL will require some "glue" chip to work over/with PCI-E. Was I wrong?

        - Gilboa
        Devel: Intel S2600C0, 2xE5-2658V2, 32GB, 6x2TB, 1x256GB-SSD, GTX1080, F32, Dell UP3216Q 4K.
        oVirt: Intel S2400GP2, 2xE5-2448L, 96GB, 10x2TB, GTX550, CentOS8.1.
        Win10: Gigabyte B85M-HD3, E3-1245V3, 32GB, 5x1TB, GTX980, Win10Pro.
        Devel-2: Asus H110M-K, i5-6500, 16GB, 3x1TB + 128GB-SSD, F32, Dell U2711.
        Laptop: ASUS Strix GL502V, i7-6700HQ, 32GB, 1TB+256GB, 1070M, F32.

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        • #5
          Originally posted by gilboa View Post

          I was under the impression CXL will require some "glue" chip to work over/with PCI-E. Was I wrong?

          - Gilboa
          I believe the pcie5 physical connection is unmodified, but a negotiation is required to determine if CXL protocol is implemented on both ends. Then there is extra handling of the coherency bias required on both sides, with the accelerator side having a much simpler design. The CXL consortium has a youtube site with an intro at the link below.

          https://youtu.be/RpAshNmpqLQ?t=1857

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          • #6
            You are correct, of-course.
            I mixed up Gen-Z and CXL.

            My bad.
            Devel: Intel S2600C0, 2xE5-2658V2, 32GB, 6x2TB, 1x256GB-SSD, GTX1080, F32, Dell UP3216Q 4K.
            oVirt: Intel S2400GP2, 2xE5-2448L, 96GB, 10x2TB, GTX550, CentOS8.1.
            Win10: Gigabyte B85M-HD3, E3-1245V3, 32GB, 5x1TB, GTX980, Win10Pro.
            Devel-2: Asus H110M-K, i5-6500, 16GB, 3x1TB + 128GB-SSD, F32, Dell U2711.
            Laptop: ASUS Strix GL502V, i7-6700HQ, 32GB, 1TB+256GB, 1070M, F32.

            Comment

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