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Intel Continues Prepping Initial Bits For Compute Express Link Device Support (CXL)

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  • Intel Continues Prepping Initial Bits For Compute Express Link Device Support (CXL)

    Phoronix: Intel Continues Prepping Initial Bits For Compute Express Link Device Support (CXL)

    Compute Express Link is the interconnect standard backed by Intel, AMD, Google, Facebook, Microsoft, Dell, and others for building off PCI Express with new CPU-to-device and CPU-to-memory capabilities. Intel's stellar open-source team has been working on plumbing the Linux kernel support for this next generation of devices...

    http://www.phoronix.com/scan.php?pag...-Link-Linux-V3

  • #2
    Maybe someone more informed can shed some light?
    I don't see how CXL provides real benefits over PCIe.
    Besides being new and shiny, latency is still in the same ballpark?

    Does CXL have same type of low latency inband control symbols like RapidIO?
    All these new protocol also share the same downside. (CXL, NvLink, SRIO).
    While sharing same platform SERDES as PCIe and bringing advantages,
    they do so with such a complex protocol (protocol stack code) that it is going to be a royal PITA.

    PCI is trivially simple in comparison while providing most of the same basic primitives.

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    • #3
      Originally posted by milkylainen View Post
      Maybe someone more informed can shed some light?
      I don't see how CXL provides real benefits over PCIe.
      Besides being new and shiny, latency is still in the same ballpark?

      Does CXL have same type of low latency inband control symbols like RapidIO?
      All these new protocol also share the same downside. (CXL, NvLink, SRIO).
      While sharing same platform SERDES as PCIe and bringing advantages,
      they do so with such a complex protocol (protocol stack code) that it is going to be a royal PITA.

      PCI is trivially simple in comparison while providing most of the same basic primitives.
      My understanding is that CXL basically adds cache coherent load/store on top of PCIe. So if you just need to read/write a little bit here and there it ought to be faster than setting up DMA operations which AFAIU is how PCIe data transfers are done today. I'm not an expert on PCI so this might all the wrong..

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      • #4
        Originally posted by jabl View Post

        My understanding is that CXL basically adds cache coherent load/store on top of PCIe. So if you just need to read/write a little bit here and there it ought to be faster than setting up DMA operations which AFAIU is how PCIe data transfers are done today. I'm not an expert on PCI so this might all the wrong..
        Well no. It's not the only way to move data over PCI. People just assume that you transfer stuff via DMA.

        PCI has always had bus snooping. But now they've given it a shiny name?
        In the old days it was called "VGA palette snooping". But snooping on PCI is generic.
        I've used snooping on PCI to speed up handling. Without the need of obtrusive DMA controllers.
        I think DMA is stupid and needs to go away.

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