Intel ISPC 1.13 Compiler Brings Performance Boost To AVX-512 Systems

[phoronix]

Phoronix: Intel ISPC 1.13 Compiler Brings Performance Boost To AVX-512 Systems

Intel's ISPC compiler (Implicit SPMD Program Compiler) for targeting its C-based single-program, multiple data language is out now with a new feature release...

http://www.phoronix.com/scan.php?page=news_item&px=Intel-ISPC-1.13-Compiler

[Aryma]

why there are not too many CPU support AVX-512 just like intel TSX ?

[ssokolow]

why there are not too many CPU support AVX-512 just like intel TSX ?

Because it's a relatively recent extension and Intel has a history of having a dozen different SKUs so you have to pay extra for each CPU feature you want?

[Spacefish]

why there are not too many CPU support AVX-512 just like intel TSX ?

TSX was broken for the first few generations and is broken again by the new speculative executions, where the mitigation is slower than just disabling TSX..

AVX-512, it would be possible for intel to implement it on low end SKUs, however you won´t really benefit from it.. There are some things:
- Running AVX-512 instructions leads to downclocking of your CPU as the AVX instructions are not stable at full operating frequency, this downclocking affects other instructions as well!
- Your system needs to save all AVX-512 registers when doing a context switch, which is a large overhead
- Especially with lower end SKUs you typically will run into memory bandwidth issues, as the execution unit will just starvate while it´s waiting for data from RAM.. Intel isn´t known for there large cache sizes either..

In the end if your algorithm can use AVX-512 it is typically parallelizable, so you can just split it into multiple threads and run them on HT cores with AVX-256 and the performance will be pretty good as well!

Also keep in mind: There is no AVX-512 per se, there are multiple different instruction set extensions defined in AVX-512 not all of them are implemented in all of the AVX-512 Intel CPUs.. Furthermore some instructions require more clock cycles and some less depending on architecture (Tiger Lake vs Skylake vs Ice Lake)

[pbrubaker]

- Running AVX-512 instructions leads to downclocking of your CPU as the AVX instructions are not stable at full operating frequency, this downclocking affects other instructions as well!

This isn't quite right. Replace "instructions" with "full width regsiters" then it's correct. You can use (most) AVX-512 instructions on 256-bit registers without a change in freq/power.

- Especially with lower end SKUs you typically will run into memory bandwidth issues, as the execution unit will just starvate while it´s waiting for data from RAM.. Intel isn´t known for there large cache sizes either..

It's possible to saturate the memory bandwidth with AVX2 as well.

IMO, the main benefit of AVX-512 is (aside from new instructions.) The built in understanding of masking. It makes things like shuffles and blends so much more powerful and easier to do.