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An Introduction To Intel's Tremont Microarchitecture

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  • #11
    Originally posted by davidbepo View Post

    (X) doubt
    this is ivy bridge level
    But recent ARM processors have a IPC equal or higher than Skylake.
    The Apple A12 "Bionic" is a little beast.

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    • #12
      Originally posted by Alex/AT View Post
      Fortunately, the typical number of different tasks running on modern general purpose CPU is more than one.
      It's 2019. DOS and likes are way in the past.
      Yes multi-tenancy is important, but if you have critical tasks that aren't embarassingly parallel we still have to deal Amdahl's law and therefore single-thread performance is still relevant.

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      • #13
        What's up with that decoder's width?

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        • #14
          This looks pretty damn powerful for a low-power optimized CPU. Maybe AMD should also make a low-power and low-cost design, possibly reusing some Zen building blocks. Previous low-power AMD architectures were quite popular after all, especially Jaguar.

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          • #15
            Originally posted by Alex/AT View Post
            Design target: single-thread performance.
            Someone tell them it's 2019 already.
            Absolutely rubbish statement. Ask any ASIC CPU engineer or any CPU architect.

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            • #16
              Originally posted by Space Heater View Post

              Yes multi-tenancy is important, but if you have critical tasks that aren't embarassingly parallel we still have to deal Amdahl's law and therefore single-thread performance is still relevant.
              Not just relevant. It's _the_ metric. Multicore is more or less a tack-on once you've taken the step (not really, but you get the point).
              Single-threaded performance is hard.
              Multiple cores do not scale forever on arbitrary problems either.
              The only reason we have multicore solutions is because single threaded performance is hard.
              If you could do the performance of all the cores in one thread with the same power envelope you could do away with SMP, Lowlevel contention, Cache coherency etc.
              A shitload of power goes to just keeping state in multicore solutions. Both in hardware and software.
              Obviously any magically fast singlecore won't happen so we deal with multicores.

              But saying that "single threaded performance does not matter" is equal to having no clue.
              Last edited by milkylainen; 10-24-2019, 05:10 PM.

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              • #17
                Originally posted by Alex/AT View Post
                Fortunately, the typical number of different tasks running on modern general purpose CPU is more than one.
                It's 2019. DOS and likes are way in the past.
                There are lot's of workloads that are single core by nature or where parallelization increases too much latency. Running "more than one task" is not decremental to a high single core performant CPU.

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                • #18
                  Originally posted by c117152 View Post
                  What's up with that decoder's width?
                  Can you elaborate that question a bit please?

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                  • #19
                    Originally posted by Space Heater View Post

                    Single-thread performance still matters in 2019, it's unfortunately not the case that every task can be parallelized to the nth degree.
                    Exactly! And especially for things like emulation.

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                    • #20
                      Originally posted by uid313 View Post

                      But recent ARM processors have a IPC equal or higher than Skylake.
                      The Apple A12 "Bionic" is a little beast.
                      Where is my 4.0GHz ARM processor?!

                      (also, they suck at tasks like compiling and video decoding...)

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