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Western Digital To Begin Shipping Devices Using RISC-V

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  • #11
    Originally posted by GI_Jack View Post
    Not surprised. I would not be surprised if MIPS-V takes a pretty big chunk of the low end embedded market, such as drive controllers, and such. I eventually see it competing with mid-range ARM chips in the long run, perhaps eventually the high end of ARM.
    Same.
    Seeing what RISC-V microcontrollers can do already, and knowing that they offer the ability to customize the microcontroller to the workload far more than ARM cores (which is very cool for microcontrollers), that's going to kick ARM around quite a bit.

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    • #12
      Originally posted by audi100quattro View Post
      I guess the first processor to be open source was Sparc T1/T2, OpenPower is open if you pay enough AFAIK. There have been hobbyist cores since, but RISC-V is the first one to really be picked up by industry/academia/startups/consumer (as softcores in FPGAs for now). Thanks UCB/Team!

      Edit: OpenRISC was before Sparc T1/T2: https://www.eetimes.com/document.asp?doc_id=1214097
      J-core has been shipping production chips for a while now [1]. They also had the advantage of exiting compiler/kernel infrastructure due to is being a clean room implementation of an existing defunct chip. They also have plans for a kickstarter with a pi-clone fgpa board [2], but it keeps getting delayed as they are already busy with their existing business.

      [1] http://j-core.org/
      [2] http://j-core.org/turtle/prototype.jpg

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      • #13
        Originally posted by GunpowaderGuy View Post
        hope they implement the fp16 extensions for ai , and or release high end ( many cores ) models without floating point ( for binarized networks )
        I kind of hope not. That is what let to it being so hard to support MIPS and early ARM models. You end up not being able to support it in generic code because you can't rely on the presence of any basic feature. And then it doesn't get used many places because most frameworks doesn't support it, or doesn't support it well.

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        • #14
          I really dont see much if a future here for RISC-V. Maybe a decade ago it might have had a chance but the industry will slowly take focus off the CPU complex to focus on hardware that offers a bigger gain. AI acceleration is one example where there are plenty of architectures to consider.

          It isnt an issue of RISC-V being good or bad, rather it is the issue of where does a company focus its engineering teams. ARM cores are pretty much a done deal these days so do you waste time on another core when the differentiator will be in specialized hatdware. I just dont see the motivation for most manufactures.

          Now as an end user i do see things differently. Ive been on the look out fir a decent ARM based laptop for some time now. The problem is nothing has raised its hand and displayed a credible design. If no one can deliver a competitive ARM based laptop i see even less happening with RISC-V. Desktops would be even farther off. As much as id love an alternative history is pretty bleak here.

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          • #15
            "We are moving beyond just storing data to now creating entire environments that will enable users to realize the value and possibilities of their data."
            Oh boy do I hate corporate PR barf.

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            • #16
              Originally posted by starshipeleven View Post
              Open does not automatically mean "gratis".
              RISC-V is an ISA, commercial RISC-V designs are is still going to have some kind of license so the designers can be paid, and there is nothing wrong in that.

              The main reason everyone apart from Intel is getting onboard of RISC-V train is because it's a better ISA, and because every company can easily (relatively speaking) design his own processor tailored to his workload with it, unlike with current ISAs that are mostly stuck on general-purpose designs because there is only ONE designer that wants to sell the same designs to everyone.

              And this is what WDC also says https://www.wdc.com/about-wd/newsroo...ironments.html

              The “general-purpose” technologies and architectures that have been in place for decades are reaching their limits of scalability, performance and efficiency. General-purpose workloads that are supported by general-purpose architectures typically have a uniform ratio of processing resources, such as operating system (OS) processing, specialty offload processing, memory, data storage and interconnect. As Big Data gets bigger and faster, and Fast Data gets faster and bigger, the "one size fits all" approach of general-purpose computing is failing to meet the increasingly diverse application workloads of our data-centric world.
              Well, ideally all RISC-V designs are fully open and anyone can pay any fab to make them. That would create the most competition, which would give all buyers the best value for their money.

              But to your point, that's not a practical solution. If RISC-V was all-open-all-the-time a lot of the big players probably wouldn't invest any resources in it because they don't want to share some of their core algorithms and design. What we have now is the option that moves RISC-V forward - an open core anyone can use, with the option for proprietary extensions. If we're lucky, enough good options will get added to the core that skipping the proprietary versions won't be a problem.

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              • #17
                Originally posted by Michael_S View Post
                Well, ideally all RISC-V designs are fully open and anyone can pay any fab to make them. That would create the most competition, which would give all buyers the best value for their money.
                That's... kinda like this, but with companies, not normal people.

                It's already ridicolously complex with software, no real user will be able to do his own hardware designs, regardless of the fact that you can't just call up GlobalFoundries to print 5 ICs just for you at an affordable price.

                What we have now is the option that moves RISC-V forward - an open core anyone can use, with the option for proprietary extensions. If we're lucky, enough good options will get added to the core that skipping the proprietary versions won't be a problem.
                RISC-V isn't a physical IC design, it is an ISA. There are design examples with a permissive license, sure, but how the hardware actually works beyond that can (and probably will) be licensed, especially if we talk of high-performance parts.

                The main interesting thing of RISC-V for small customers is that proprietary hardware products can compete on an even field, as they all have the same architecture. It's like if every company could make x86 processors without asking Intel first. Architecture wars finally over, this is especially good for proprietary applications.

                The consumers (software users) will no more be locked to a specific hardware designer/vendor, as their code will work mostly fine on any processor as long as hardware specs are ok.

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                • #18
                  Originally posted by GunpowaderGuy View Post
                  i wonder what kind of modifications ( extensions ) risc V can still receive without breaking compatiblity for the most part ( too late for breaking changes , right ? )
                  RISC-V has been designed specifically for enabling various extensions, by leaving free opcode space in the base ISA. The idea is to have a common base ISA, and hence share all the work for OS and toolchain support, and then add various application-specific acceleration extensions with very little effort compared to doing everything from scratch.

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                  • #19
                    As an aside, for some very interesting RISC-V work in the area of ML/AI/HPC, see the presentation by Dave Ditzel from "Esperanto" who just exited stealth mode. Presentation slides aren't online yet, but some notes from one of the lowrisc guys: http://www.lowrisc.org/blog/2017/11/...kshop-day-one/

                    In short, they are planning a device containing 16 "high-performance" cores and 4096(!!!) simple in-order cores with the vector extensions, some machine learning extensions, and multiple threads. If successful, this is a monster for HPC/ML style workloads..

                    That Dave Ditzel character, BTW, was apparently one of the founders of Transmeta, who used to employ Linus Torvalds back in the day.

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                    • #20
                      After losing the Toshiba bid they were itching to get into the CPU world.

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