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Some Early AMD Ryzen Threadripper 1950X Linux Benchmarks

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  • #31
    Originally posted by profoundWHALE View Post
    If my memory serves me well, which it usually doesn't, an EPYC chip would be a threadripper but with all 4 dies working
    Your memory mostly served you well. Epyc is almost literally a doubled-up TR. Double the cores, double the dies, double the PCIe lanes, etc. What isn't doubled are frequencies (duh), memory channels, and (to my knowledge) L3 cache. The L3 is still higher, but I don't think it is doubled.

    On a side note, what I find a bit interesting are the 8c/16t Epycs (yes, those will exist), because what those imply is 2 active cores per die. Threadripper doesn't have a configuration like that, probably because it wouldn't sell well. After all, who wants a 4c/8t CPU with such an expensive motherboard? So, they're probably using all those binned dies for low-end Epycs, where people want all the abundant PCIe lanes but don't care so much about raw CPU performance. These parts are also clocked pretty low.
    Last edited by schmidtbag; 25 August 2017, 03:18 PM.

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    • #32
      I can tell you who wants CPUs like that - all the engineers that use CFD and FEM codes since they're heavy memory bound. 8 cores with 8 memory channels is a blessing for them. Not to mention per-core licensing models

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      • #33
        Originally posted by schmidtbag View Post
        Your memory mostly served you well. Epyc is almost literally a doubled-up TR. Double the cores, double the dies, double the PCIe lanes, etc. What isn't doubled are frequencies (duh), memory channels, and (to my knowledge) L3 cache. The L3 is still higher, but I don't think it is doubled.

        On a side note, what I find a bit interesting are the 8c/16t Epycs (yes, those will exist), because what those imply is 2 active cores per die. Threadripper doesn't have a configuration like that, probably because it wouldn't sell well. After all, who wants a 4c/8t CPU with such an expensive motherboard? So, they're probably using all those binned dies for low-end Epycs, where people want all the abundant PCIe lanes but don't care so much about raw CPU performance. These parts are also clocked pretty low.
        Makes a lot of sense.

        I've gotten to see one. I didn't install it, but I watched the dude who did it. It kinda feels like "big tin", if you know what that means. It doesn't feel like it belongs in a gamer's machine.
        Last edited by duby229; 25 August 2017, 05:32 PM.

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        • #34
          Originally posted by profoundWHALE View Post

          If my memory serves me well, which it usually doesn't, an EPYC chip would be a threadripper but with all 4 dies working
          Indeed it doesn't. Threadripper has 2 "Dummy" dies. Just empty components of the CPU. They are meant to add support for such a huge die area.

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          • #35
            This is the review that really matter for me. Can't wait to see the 11 pager Micheal.

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            • #36
              I think it would be interesting if AMD used all the extra empty space for a ThreadRipper+ version with giant L4 caches... like 512MB or 1GB just obscene cache sizes. Or maybe 1GB cache + 32Gb HBM2... on the chip package.... then you could actually make an ITX system with ThreadRipper since you wouldn't need ram slots.

              I'm my case, Ryzen 7 is already overkill and I have trouble keeping it busy... but a ThreadRipper + gigantic caches would bring a tear to the eyes of many. Call it the OverKiller or something like that... I just feel like they should be doing something crazy in all that empty space on the TR package.
              Last edited by cb88; 25 August 2017, 06:21 PM.

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              • #37
                Michael, is it possible to run benchmarks in parallel? As in, running multiple tests concurrently. Say for example, audio/video encoding and file compression. I know it complicates the benchmarking process exponentially, but I think with chips like Threadripper and the Core i9s, the real world use for these chips will indeed include such mixed concurrent workloads. Mega-tasking I think it's called.. maybe a survey of Phoronix users to ask what benchmarks should be combined to represent their use cases? That might help deciding on some sort of standard "mega-tasking" test profile(s). Would definitely be interesting! In a mega-tasking test, I'd like to see AVX and non-AVX combined on Skylake-X and Threadripper.
                Last edited by lem79; 25 August 2017, 07:59 PM. Reason: Clearer language

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                • #38
                  Originally posted by lem79 View Post
                  Michael, is it possible to run benchmarks in parallel? As in, running multiple tests concurrently. Say for example, audio/video encoding and file compression. I know it complicates the benchmarking process exponentially, but I think with chips like Threadripper and the Core i9s, the real world use for these chips will indeed include such mixed concurrent workloads. Mega-tasking I think it's called.. maybe a survey of Phoronix users to ask what benchmarks should be combined to represent their use cases? That might help deciding on some sort of standard "mega-tasking" test profile(s). Would definitely be interesting! In a mega-tasking test, I'd like to see AVX and non-AVX combined on Skylake-X and Threadripper.
                  phoronix-test-suite stress-run (http://www.phoronix.com/scan.php?pag...ite+stress-run ) runs multiple tests concurrently.
                  Michael Larabel
                  https://www.michaellarabel.com/

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                  • #39
                    Originally posted by vsteel View Post

                    I doubt they are blanks. In the chip world they would be foolish to be cutting up good silicon to fill the spaces with. I would be they take dead die that failed at probe and pull them and just them as spacers. So while they wouldn't be blank die, they would be about as useful.

                    You want to get as many useful die on a wafer as possible and when you have blanks in the mix it would mess up etch uniformity and mess some with the CMP.

                    I know just a small detail but I do really get a kick out of the stories on windows sites and the people who comment that talk about making chips, you can tell most have no idea what they are doing and the ones that semi know most of them are in college or professors that have not been in the real world and don't realize how far off their ideas are. (Yes I work for a company that makes chips at small geometries and high speed) Though not all are that way, there are some you can tell that know their stuff.
                    This isn't true. AMD has officially said multiple times the other 2-dies present on the Threadripper package are simply blank pieces of silicon used as structural spacers for the IHS. AMD's 8-core "Zeppelin" die; which is used in the ENTIRE Zen stack at the moment (will be till the Raven Ridge APU comes out later this year), is currently getting 80%+ all 8-cores functional yields according to AMD & GlobalFoundries' most recently released numbers. That means there are practically 0 chips that are so defected as to be unsellable. They are packaging and selling pretty much every single Zeppelin die that comes off of GloFo's lines. With this being the case it makes absolutely NO sense to use defective Zeppelin's instead of blank silicon for the IHS support spacers, rather than selling that defective die as an R5/R3 or whatever.

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                    • #40
                      Originally posted by Michael View Post

                      phoronix-test-suite stress-run (http://www.phoronix.com/scan.php?pag...ite+stress-run ) runs multiple tests concurrently.
                      Ah very nice, thanks. Seems like you could easily do some mega-tasking benchmarks.. is that on the agenda for your Threadripper, Core i9 and Xeons? I've seen at least one review (AdoredTV) where Threadripper mega-tasks like a boss.

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