Announcement

Collapse
No announcement yet.

New Ryzen Is Running Solid Under Linux, No Compiler Segmentation Fault Issue

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • #71
    Originally posted by vw_fan17 View Post
    Almost sounds like they've identified an issue where some chips (due to manufacturing variability?) lose signal integrity under certain conditions, and eventually cause a memory-access issue or similar? This testing stuff makes it sound like they're going through their inventory until they find a "silicon lottery" chip and shipping that out to everyone who complains. Not sure if I'm happy or sad about that.
    This is what looks like is happening - my assumption is that when the 1725+ chips make it to the stores, they'd still have problems unless AMD starts beefing up their testing / binning process. Given that they haven't said much - pretty sure people will still be playing silicon lottery with retail purchases.

    The 1725+ chips are hard to find (if any are out there on the shelves), even Newegg - a high volume dealer (still shipping 09 week chips).
    Last edited by Funks; 29 August 2017, 06:26 PM.

    Comment


    • #72
      If it was silicon lottery related to power .. shouldn't undervolting make this issue much worse/more frequent?

      Comment


      • #73
        lem79
        The only setting that are confirmed by users to have an impact are
        • disable µOP cache - makes the problem go away, or at least much harder to trigger
        • disable SMT - increases time between segfaults from a couple minutes before, to at least several hours afterwards
        • disable kernel ASLR - similar as above


        Not confirmed, but some individuals report improvement while others don't:
        • disable XMP profiles and relax memory clock/timings to safe values
        • enable LLC (load line calibration)
        • increase CPU SoC voltage

        (Edit: thanks Anty for pointing out that it is not CPU Vcore, but actually SoC voltage where an increase might have an effect)
        Last edited by chithanh; 31 August 2017, 09:31 AM.

        Comment


        • #74
          Not increase CPU voltage but SOC voltage. CPU settings seem irrelevant. SOC makes big change - allows to use even OC memory GCC stable. But most people just whine loudly instead of changing few things in BIOS.

          Comment


          • #75
            Thanks for the summary. Like everyone else I'm interested to know the truth. Seems strange that so many things can impact the bug .. doesn't really look power related if increasing voltage doesn't reliably fix it in all cases.

            Comment


            • #76
              Oh, I didn't expect to see the error that fast...
              [loop-10] TIME TO FAIL: 95 s

              Comment


              • #77
                Anyone had done a rma? How it works? Do you have to send the cpu to amd? If so... if you are outside usa, do you have to do a international shipment and send the cpu to usa?

                Comment


                • #78
                  So, I received my RMA yesterday and it has been running for 18+ hours with no segfault issues. The RMA process was pretty pleasant and within a week (after debugging with AMD support and starting the RMA process) I was back up and running. The chip I sent in for RMA was dated 1708PGT, while my new one with no segfault issues has 1728SUS.

                  Comment


                  • #79
                    So, I received my RMA yesterday and it has been running for 18+ hours with no segfault issues. The RMA process was pretty pleasant and within a week (after debugging with AMD support and starting the RMA process) I was back up and running. The chip I sent in for RMA was dated 1708PGT, while my new one with no segfault issues has 1728SUS.

                    Comment


                    • #80
                      So this problem is still a thing? Guess I will just buy the CPU for my build last. Really wanted a new Ryzen rig up and running before Christmas.

                      Comment

                      Working...
                      X