Announcement

Collapse
No announcement yet.

RISC-V Support Continues Advancing For LLVM

Collapse
X
  • Filter
  • Time
  • Show
Clear All
new posts

  • RISC-V Support Continues Advancing For LLVM

    Phoronix: RISC-V Support Continues Advancing For LLVM

    For those interested in the RISC-V open-source, royalty-free RISC-V instruction set architecture, the LLVM compiler support for it continues advancing...

    http://www.phoronix.com/scan.php?pag...-2017-Progress

  • #2
    Typo:

    Originally posted by phoronix View Post
    Alex Bradbury gas written a status update concerning the RISC-V LLVM support.

    Comment


    • #3
      When does it have something that can compete with Raspberry Pi?

      Not a 256 MB single-core SoC.
      A 2 GHz quad-core or octa-core SoC with 2-6 GB RAM and Gigabit Ethernet with USB Type-C.

      Comment


      • #4
        Originally posted by uid313 View Post
        When does it have something that can compete with Raspberry Pi?

        Not a 256 MB single-core SoC.
        A 2 GHz quad-core or octa-core SoC with 2-6 GB RAM and Gigabit Ethernet with USB Type-C.
        Yeah, that's what I keep thinking, and it's why I chose to invest in a Talos II (based on POWER9, which exists today) as a libre-friendly computer instead of waiting longer for a usable general-purpose computer with RISC-V (and like permissive licenses in software, there is no guarantee that those platforms will be any less closed down than your typical ARM SoC).

        Comment


        • #5
          Originally posted by uid313 View Post
          When does it have something that can compete with Raspberry Pi?

          Not a 256 MB single-core SoC.
          A 2 GHz quad-core or octa-core SoC with 2-6 GB RAM and Gigabit Ethernet with USB Type-C.
          It's important to realize, that RISC V is an ISA. An ISA is not a CPU.
          While a solid ISA is nice to have, the more important part, especially today, is the actual CPU architecture which is largely unrelated to the ISA.

          So there is no point in guessing the performance of RISC V without having a concrete implementation. Implementations will vary be a huge margin even if they use nothing but valid RISC V instructions. The code in LLVM only translates to RISC V instructions, it does not do any optimization whatever, because there is not yet a widely available hardware implementation of the ISA.

          It is highly unlikely that we will see any kind of high-end CPU implementing RISC V in the next decade. It is highly likely that RISC V implementations will be tiny CPUs for ultra-low-power embedded systems, comparable to microcontroller-like ARM cores like the Cortex-M0, for the years to come.

          Comment


          • #6
            Originally posted by tg-- View Post
            It's important to realize, that RISC V is an ISA. An ISA is not a CPU.
            While a solid ISA is nice to have, the more important part, especially today, is the actual CPU architecture which is largely unrelated to the ISA.
            To some degree, the ISA and architecture go hand and hand. An VLIW architecture would require an ISA that can bundle multiple operations per instructions. A RISC architecture will have a relatively small and uniform instruction set. An alien like the mill, has to have an alien ISA. You cannot have a RISC like ISA for a VLIW architecture. A RISC architecture would not be compatible with an ISA that is designed for a CISC architecture.

            It is important to have a well designed ISA for your architecture, otherwise you would end up adding extra hardware to deal with it, adding extra steps in the CPU pipeline, or worse stalling functional units.

            Comment


            • #7
              Originally posted by paulpach View Post

              To some degree, the ISA and architecture go hand and hand. An VLIW architecture would require an ISA that can bundle multiple operations per instructions. A RISC architecture will have a relatively small and uniform instruction set. An alien like the mill, has to have an alien ISA. You cannot have a RISC like ISA for a VLIW architecture. A RISC architecture would not be compatible with an ISA that is designed for a CISC architecture.

              It is important to have a well designed ISA for your architecture, otherwise you would end up adding extra hardware to deal with it, adding extra steps in the CPU pipeline, or worse stalling functional units.
              All modern architectures since the late 90s have been internally VLIW, that doesn't make it a good ISA. It is much better to let the CPU package the microcodes that can be executed in parallel together than trying to do it in advance with a compiler. And since there is that decoding and micro-op scheduling anyway, the input ISA doesn't matter much. What is important is features, and secondarily making it easy for the architecture to decode ahead (with fixed instruction size for instance).

              Comment


              • #8
                Originally posted by tg-- View Post

                It is highly unlikely that we will see any kind of high-end CPU implementing RISC V in the next decade. It is highly likely that RISC V implementations will be tiny CPUs for ultra-low-power embedded systems, comparable to microcontroller-like ARM cores like the Cortex-M0, for the years to come.
                That is fine, RISC-V is definitely a long term project. Its kinda funny some people have zero patience. There are a certain group of people who feel that if a piece of tech isn't immediately getting them more fraps in their latest video game it needs to be abandoned immediately.

                Next step after having a Free ISA, is to starting making some Free reference CPUs which are also Free, as in speech. Combine with OpenEC, Factory coreboot, and it wouldn't be too too hard for a mostly free dev board/computer.

                Comment


                • #9
                  Sounds like RISC-V will have day one Rust support then, once the hardware starts getting mass produced.

                  Comment


                  • #10
                    Originally posted by tg-- View Post
                    It's important to realize, that RISC V is an ISA. An ISA is not a CPU.
                    While a solid ISA is nice to have, the more important part, especially today, is the actual CPU architecture which is largely unrelated to the ISA.

                    So there is no point in guessing the performance of RISC V without having a concrete implementation. Implementations will vary be a huge margin even if they use nothing but valid RISC V instructions. The code in LLVM only translates to RISC V instructions, it does not do any optimization whatever, because there is not yet a widely available hardware implementation of the ISA.
                    The RISC-V Rocket architecture is available, and you can buy the SiFive HiFive1 with it and develop and benchmark real hardware for less than $100. I would call that available enough for at least some optimization.

                    Originally posted by tg-- View Post
                    It is highly unlikely that we will see any kind of high-end CPU implementing RISC V in the next decade. It is highly likely that RISC V implementations will be tiny CPUs for ultra-low-power embedded systems, comparable to microcontroller-like ARM cores like the Cortex-M0, for the years to come.
                    This is the sad truth though.
                    The RISC-V BOOM architecture is still in development and will probably be a while longer until we will see mass-produced implementations of it and after that we'll need to wait a lot longer until it will be competetive.

                    Comment

                    Working...
                    X